{"id":421502,"date":"2024-10-20T06:36:35","date_gmt":"2024-10-20T06:36:35","guid":{"rendered":"https:\/\/pdfstandards.shop\/product\/uncategorized\/bs-en-iec-62878-2-52019-2\/"},"modified":"2024-10-26T12:22:14","modified_gmt":"2024-10-26T12:22:14","slug":"bs-en-iec-62878-2-52019-2","status":"publish","type":"product","link":"https:\/\/pdfstandards.shop\/product\/publishers\/bsi\/bs-en-iec-62878-2-52019-2\/","title":{"rendered":"BS EN IEC 62878-2-5:2019"},"content":{"rendered":"

This part of IEC 62878 specifies requirements based on XML schema that represents a design data format for device embedded substrate, which is a board comprising embedded active and passive devices whose electrical connections are made by means of a via, electroplating, conductive paste or printing of conductive material.<\/p>\n

This data format is to be used for simulation (e.g. stress, thermal, EMC), tooling, manufacturing, assembly, and inspection requirements. Furthermore, the data format is used for transferring information among printed board designers, printed board simulation engineer, manufacturers, and assemblers.<\/p>\n

This part of IEC 62878 applies to substrates using organic material. It neither applies to the re-distribution layer (RDL) nor to the electronic modules defined as M-type business model in IEC 62421.<\/p>\n

PDF Catalog<\/h4>\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
PDF Pages<\/th>\nPDF Title<\/th>\n<\/tr>\n
2<\/td>\nundefined <\/td>\n<\/tr>\n
5<\/td>\nCONTENTS <\/td>\n<\/tr>\n
8<\/td>\nFOREWORD <\/td>\n<\/tr>\n
10<\/td>\n1 Scope
2 Normative references
3 Terms and definitions <\/td>\n<\/tr>\n
13<\/td>\n4 Data definition
4.1 Flow chart design of device embedded substrate <\/td>\n<\/tr>\n
14<\/td>\n4.2 Applicable range
4.2.1 Product
Figures
Figure 1 \u2013 Flow chart of design of device embedded substrate <\/td>\n<\/tr>\n
15<\/td>\n4.2.2 Process
Figure 2 \u2013 General structure of device embedded substrate <\/td>\n<\/tr>\n
16<\/td>\n4.3 Features
4.3.1 General
4.3.2 Device embedded substrate structure
Tables
Table 1 \u2013 Required information <\/td>\n<\/tr>\n
17<\/td>\n4.3.3 SiP interposer structure
Figure 3 \u2013 Example of device embedded substrate structure
Figure 4 \u2013 Examples of SiPs <\/td>\n<\/tr>\n
18<\/td>\n4.3.4 Virtual layer description
4.3.5 Terminal structure and embedded device structure including an SiP
4.3.6 Total design data of an SiP and device embedded substrate
Figure 5 \u2013 Example of virtual layer description
Figure 6 \u2013 Terminal structure <\/td>\n<\/tr>\n
19<\/td>\n4.4 Data description summary
4.4.1 Type of data and structures
Figure 7 \u2013 Structure of SiP on a device embedded substrate <\/td>\n<\/tr>\n
20<\/td>\nTable 2 \u2013 List of data <\/td>\n<\/tr>\n
21<\/td>\n4.4.2 File structure
Figure 8 \u2013 Data structure <\/td>\n<\/tr>\n
22<\/td>\n4.5 3D expression
4.5.1 General
4.5.2 Coordinates
Figure 9 \u2013 One file structure (recommended)
Figure 10 \u2013 Two file structure <\/td>\n<\/tr>\n
23<\/td>\n4.5.3 Position description
4.5.4 Relation between coordinate origin and board position
Figure 11 \u2013 Definition of coordinates
Figure 12 \u2013 Position definition <\/td>\n<\/tr>\n
24<\/td>\n4.6 Layer concept
4.7 Substrate data
4.7.1 General
Figure 13 \u2013 Relation between coordinates and board position
Figure 14 \u2013 Layer concept <\/td>\n<\/tr>\n
25<\/td>\n4.7.2 Layer map information
Figure 15 \u2013 Layer construction <\/td>\n<\/tr>\n
26<\/td>\n4.7.3 Device arrangement information
Figure 16 \u2013 Simplified layer construction <\/td>\n<\/tr>\n
27<\/td>\nFigure 17 \u2013 Layer definition of pad connection
Figure 18 \u2013 Layer definition of via connection <\/td>\n<\/tr>\n
28<\/td>\n4.7.4 Basic figures
Figure 19 \u2013 Rotation direction on X, Y, and Z axes <\/td>\n<\/tr>\n
29<\/td>\nFigure 20 \u2013 Point <\/td>\n<\/tr>\n
30<\/td>\nFigure 21 \u2013 Area
Figure 22 \u2013 Lines <\/td>\n<\/tr>\n
31<\/td>\nFigure 23 \u2013 Letters
Figure 24 \u2013 Letter shape <\/td>\n<\/tr>\n
32<\/td>\nFigure 25 \u2013 Bonding wire information
Figure 26 \u2013 Semi-sphere <\/td>\n<\/tr>\n
33<\/td>\nFigure 27 \u2013 Truncated pyramid
Figure 28 \u2013 Via <\/td>\n<\/tr>\n
34<\/td>\n4.7.5 Net information
Figure 29 \u2013 Device definition
Figure 30 \u2013 Group <\/td>\n<\/tr>\n
35<\/td>\n4.7.6 Artwork information
4.7.7 Package information
Figure 31 \u2013 Data structure of net information <\/td>\n<\/tr>\n
36<\/td>\n4.7.8 External port information
4.7.9 Internal port information
4.7.10 User expansion information
4.8 Defined data
4.8.1 General
4.8.2 Layer definition <\/td>\n<\/tr>\n
37<\/td>\n4.8.3 Land definition
Figure 32 \u2013 Relation of layer definition data <\/td>\n<\/tr>\n
38<\/td>\n4.8.4 Via definition
Figure 33 \u2013 Land definition <\/td>\n<\/tr>\n
39<\/td>\n4.8.5 Device definition
Figure 34 \u2013 Relation between hole information and land information <\/td>\n<\/tr>\n
40<\/td>\n4.8.6 User expansion definition
Figure 35 \u2013 Device with internal connection information
Figure 36 \u2013 Device without internal connection information <\/td>\n<\/tr>\n
41<\/td>\n5 Data organization and data description based on XML schema
5.1 General
5.2 Data organization of Example 1
Figure 37 \u2013 Cross sectional view of Example 1
Figure 38 \u2013 Data organization of Example 1 <\/td>\n<\/tr>\n
42<\/td>\n5.3 Data description of layer stack-up
Figure 39 \u2013 Data descripion of Example 1 <\/td>\n<\/tr>\n
43<\/td>\nFigure 40 \u2013 Layer structure of Example 1 <\/td>\n<\/tr>\n
45<\/td>\nFigure 41 \u2013 Data description of layer stack-up <\/td>\n<\/tr>\n
46<\/td>\n5.4 Data description of device
Figure 42 \u2013 Configuration of device 1 <\/td>\n<\/tr>\n
47<\/td>\nFigure 43 \u2013 Data description of device 1 <\/td>\n<\/tr>\n
48<\/td>\nFigure 44 \u2013 Configuration of device 2 <\/td>\n<\/tr>\n
49<\/td>\nFigure 45 \u2013 Data description of device 2 <\/td>\n<\/tr>\n
50<\/td>\n5.5 Data organization of layer <\/td>\n<\/tr>\n
51<\/td>\nFigure 46 \u2013 Layer view of Example 1 <\/td>\n<\/tr>\n
53<\/td>\n5.6 Data description of via
Figure 47 \u2013 Data description of layers <\/td>\n<\/tr>\n
54<\/td>\n5.7 Data description of land
Figure 48 \u2013 Type of vias
Figure 49 \u2013 Data description of vias <\/td>\n<\/tr>\n
55<\/td>\nFigure 50 \u2013 Type of lands
Figure 51 \u2013 Data description of lands <\/td>\n<\/tr>\n
56<\/td>\nBibliography <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":"

Device embedding assembly technology – Guidelines. Implementation of a 3D data format for device embedded substrate<\/b><\/p>\n\n\n\n\n
Published By<\/td>\nPublication Date<\/td>\nNumber of Pages<\/td>\n<\/tr>\n
BSI<\/b><\/a><\/td>\n2019<\/td>\n58<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n","protected":false},"featured_media":421512,"template":"","meta":{"rank_math_lock_modified_date":false,"ep_exclude_from_search":false},"product_cat":[2641],"product_tag":[],"class_list":{"0":"post-421502","1":"product","2":"type-product","3":"status-publish","4":"has-post-thumbnail","6":"product_cat-bsi","8":"first","9":"instock","10":"sold-individually","11":"shipping-taxable","12":"purchasable","13":"product-type-simple"},"_links":{"self":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product\/421502","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product"}],"about":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/types\/product"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media\/421512"}],"wp:attachment":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media?parent=421502"}],"wp:term":[{"taxonomy":"product_cat","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_cat?post=421502"},{"taxonomy":"product_tag","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_tag?post=421502"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}