{"id":229005,"date":"2024-10-19T14:53:43","date_gmt":"2024-10-19T14:53:43","guid":{"rendered":"https:\/\/pdfstandards.shop\/product\/uncategorized\/bs-en-62680-2-12015\/"},"modified":"2024-10-25T09:01:02","modified_gmt":"2024-10-25T09:01:02","slug":"bs-en-62680-2-12015","status":"publish","type":"product","link":"https:\/\/pdfstandards.shop\/product\/publishers\/bsi\/bs-en-62680-2-12015\/","title":{"rendered":"BS EN 62680-2-1:2015"},"content":{"rendered":"

IEC 62680-2-1:2015 defines an industry-standard USB. The specification describes the bus attributes, the protocol definition, types of transactions, bus management, and the programming interface required to design and build systems and peripherals that are compliant with this standard. The goal is to enable such devices from different vendors to interoperate in an open architecture. The specification is intended as an enhancement to the PC architecture, spanning portable, business desktop, and home environments. It is intended that the specification allow system OEMs and peripheral developers adequate room for product versatility and market differentiation without the burden of carrying obsolete interfaces or losing compatibility.<\/p>\n

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PDF Pages<\/th>\nPDF Title<\/th>\n<\/tr>\n
5<\/td>\nFOREWORD <\/td>\n<\/tr>\n
7<\/td>\nINTRODUCTION <\/td>\n<\/tr>\n
8<\/td>\nCONTENTS <\/td>\n<\/tr>\n
32<\/td>\n1 Chapter 1 Introduction
1.1 Motivation
1.2 Objective of the Specification <\/td>\n<\/tr>\n
33<\/td>\n1.3 Scope of the Document
1.4 USB Product Compliance
1.5 Document Organization <\/td>\n<\/tr>\n
34<\/td>\n2 Chapter 2 Terms and Abbreviations <\/td>\n<\/tr>\n
40<\/td>\n3 Chapter 3 Background
3.1 Goals for the Universal Serial Bus
3.2 Taxonomy of Application Space
Figures
Figure 3-1 \u2013 Application Space Taxonomy <\/td>\n<\/tr>\n
41<\/td>\n3.3 Feature List <\/td>\n<\/tr>\n
43<\/td>\n4 Chapter 4 Architectural Overview
4.1 USB System Description
4.1.1 Bus Topology <\/td>\n<\/tr>\n
44<\/td>\n4.2 Physical Interface
Figure 4-1 \u2013 Bus Topology <\/td>\n<\/tr>\n
45<\/td>\n4.2.1 Electrical
4.2.2 Mechanical
4.3 Power
Figure 4-2 \u2013 USB Cable <\/td>\n<\/tr>\n
46<\/td>\n4.3.1 Power Distribution
4.3.2 Power Management
4.4 Bus Protocol
4.5 Robustness <\/td>\n<\/tr>\n
47<\/td>\n4.5.1 Error Detection
4.5.2 Error Handling
4.6 System Configuration
4.6.1 Attachment of USB Devices
4.6.2 Removal of USB Devices <\/td>\n<\/tr>\n
48<\/td>\n4.6.3 Bus Enumeration
4.7 Data Flow Types
4.7.1 Control Transfers
4.7.2 Bulk Transfers
4.7.3 Interrupt Transfers <\/td>\n<\/tr>\n
49<\/td>\n4.7.4 Isochronous Transfers
4.7.5 Allocating USB Bandwidth
4.8 USB Devices
4.8.1 Device Characterizations <\/td>\n<\/tr>\n
50<\/td>\n4.8.2 Device Descriptions
Figure 4-3 \u2013 A Typical Hub <\/td>\n<\/tr>\n
51<\/td>\nFigure 4-4 \u2013 Hubs in a Desktop Computer Environment <\/td>\n<\/tr>\n
52<\/td>\n4.9 USB Host: Hardware and Software
4.10 Architectural Extensions <\/td>\n<\/tr>\n
53<\/td>\n5 Chapter 5 USB Data Flow Model
5.1 Implementer Viewpoints
Figure 5-1 \u2013 Simple USB Host\/Device View <\/td>\n<\/tr>\n
54<\/td>\n5.2 Bus Topology
Figure 5-2 \u2013 USB Implementation Areas <\/td>\n<\/tr>\n
55<\/td>\n5.2.1 USB Host
5.2.2 USB Devices
Figure 5-3 \u2013 Host Composition <\/td>\n<\/tr>\n
56<\/td>\n5.2.3 Physical Bus Topology
Figure 5-4 \u2013 Physical Device Composition
Figure 5-5 \u2013 USB Physical Bus Topology <\/td>\n<\/tr>\n
57<\/td>\n5.2.4 Logical Bus Topology
Figure 5-6 \u2013 Multiple Full-speed Buses in a High-speed System <\/td>\n<\/tr>\n
58<\/td>\n5.2.5 Client Software-to-function Relationship
5.3 USB Communication Flow
Figure 5-7 \u2013 USB Logical Bus Topology
Figure 5-8 \u2013 Client Software-to-function Relationships <\/td>\n<\/tr>\n
59<\/td>\nFigure 5-9 \u2013 USB Host\/Device Detailed View <\/td>\n<\/tr>\n
60<\/td>\n5.3.1 Device Endpoints
Figure 5-10 \u2013 USB Communication Flow <\/td>\n<\/tr>\n
61<\/td>\n5.3.2 Pipes <\/td>\n<\/tr>\n
63<\/td>\n5.3.3 Frames and Microframes
5.4 Transfer Types <\/td>\n<\/tr>\n
64<\/td>\n5.4.1 Table Calculation Examples <\/td>\n<\/tr>\n
65<\/td>\n5.5 Control Transfers
5.5.1 Control Transfer Data Format <\/td>\n<\/tr>\n
66<\/td>\n5.5.2 Control Transfer Direction
5.5.3 Control Transfer Packet Size Constraints <\/td>\n<\/tr>\n
67<\/td>\n5.5.4 Control Transfer Bus Access Constraints <\/td>\n<\/tr>\n
68<\/td>\nTables
Table 5-1 \u2013 Low-speed Control Transfer Limits <\/td>\n<\/tr>\n
69<\/td>\n5.5.5 Control Transfer Data Sequences
Table 5-2 \u2013 Full-speed Control Transfer Limits
Table 5-3 \u2013 High-speed Control Transfer Limits <\/td>\n<\/tr>\n
70<\/td>\n5.6 Isochronous Transfers
5.6.1 Isochronous Transfer Data Format
5.6.2 Isochronous Transfer Direction
5.6.3 Isochronous Transfer Packet Size Constraints <\/td>\n<\/tr>\n
71<\/td>\nTable 5-4 \u2013 Full-speed Isochronous Transaction Limits <\/td>\n<\/tr>\n
72<\/td>\n5.6.4 Isochronous Transfer Bus Access Constraints
Table 5-5 \u2013 High-speed Isochronous Transaction Limits <\/td>\n<\/tr>\n
73<\/td>\n5.6.5 Isochronous Transfer Data Sequences
5.7 Interrupt Transfers
5.7.1 Interrupt Transfer Data Format
5.7.2 Interrupt Transfer Direction
5.7.3 Interrupt Transfer Packet Size Constraints <\/td>\n<\/tr>\n
74<\/td>\n5.7.4 Interrupt Transfer Bus Access Constraints <\/td>\n<\/tr>\n
75<\/td>\nTable 5-6 \u2013 Low-speed Interrupt Transaction Limits
Table 5-7 \u2013 Full-speed Interrupt Transaction Limits <\/td>\n<\/tr>\n
76<\/td>\nTable 5-8 \u2013 High-speed Interrupt Transaction Limits <\/td>\n<\/tr>\n
77<\/td>\n5.7.5 Interrupt Transfer Data Sequences
5.8 Bulk Transfers
5.8.1 Bulk Transfer Data Format
5.8.2 Bulk Transfer Direction
5.8.3 Bulk Transfer Packet Size Constraints <\/td>\n<\/tr>\n
78<\/td>\n5.8.4 Bulk Transfer Bus Access Constraints <\/td>\n<\/tr>\n
79<\/td>\n5.8.5 Bulk Transfer Data Sequences
Table 5-9 \u2013 Full-speed Bulk Transaction Limits
Table 5-10 \u2013 High-speed Bulk Transaction Limits <\/td>\n<\/tr>\n
80<\/td>\n5.9 High-Speed, High Bandwidth Endpoints
5.9.1 High Bandwidth Interrupt Endpoints
Table 5-11 \u2013 wMaxPacketSize Field of Endpoint Descriptor <\/td>\n<\/tr>\n
81<\/td>\n5.9.2 High Bandwidth Isochronous Endpoints
Figure 5-11 \u2013 Data Phase PID Sequence for Isochronous IN High Bandwidth Endpoints <\/td>\n<\/tr>\n
82<\/td>\n5.10 Split Transactions
5.11 Bus Access for Transfers
Figure 5-12 \u2013 Data Phase PID Sequence for Isochronous OUT High Bandwidth Endpoints <\/td>\n<\/tr>\n
83<\/td>\n5.11.1 Transfer Management
Figure 5-13 \u2013 USB Information Conversion From Client Software to Bus <\/td>\n<\/tr>\n
85<\/td>\n5.11.2 Transaction Tracking <\/td>\n<\/tr>\n
86<\/td>\nFigure 5-14 \u2013 Transfers for Communication Flows <\/td>\n<\/tr>\n
87<\/td>\n5.11.3 Calculating Bus Transaction Times
Figure 5-15 \u2013 Arrangement of IRPs to Transactions\/(Micro)frames <\/td>\n<\/tr>\n
89<\/td>\n5.11.4 Calculating Buffer Sizes in Functions and Software
5.11.5 Bus Bandwidth Reclamation
5.12 Special Considerations for Isochronous Transfers <\/td>\n<\/tr>\n
91<\/td>\n5.12.1 Example Non-USB Isochronous Application
Figure 5-16 \u2013 Non-USB Isochronous Example <\/td>\n<\/tr>\n
92<\/td>\n5.12.2 USB Clock Model <\/td>\n<\/tr>\n
93<\/td>\nFigure 5-17 \u2013 USB Full-speed Isochronous Application <\/td>\n<\/tr>\n
94<\/td>\n5.12.3 Clock Synchronization
5.12.4 Isochronous Devices <\/td>\n<\/tr>\n
95<\/td>\nTable 5-12 \u2013 Synchronization Characteristics <\/td>\n<\/tr>\n
99<\/td>\nFigure 5-18 \u2013 Example Source\/Sink Connectivity <\/td>\n<\/tr>\n
101<\/td>\nTable 5-13 \u2013 Connection Requirements <\/td>\n<\/tr>\n
102<\/td>\n5.12.5 Data Prebuffering <\/td>\n<\/tr>\n
103<\/td>\n5.12.6 SOF Tracking
5.12.7 Error Handling
Figure 5-19 \u2013 Data Prebuffering <\/td>\n<\/tr>\n
104<\/td>\n5.12.8 Buffering for Rate Matching <\/td>\n<\/tr>\n
105<\/td>\nFigure 5-20 \u2013 Packet and Buffer Size Formulas for Rate-matched Isochronous Transfers <\/td>\n<\/tr>\n
106<\/td>\n6 Chapter 6 Mechanical
6.1 Architectural Overview
6.2 Keyed Connector Protocol
Figure 6-1 \u2013 Keyed Connector Protocol <\/td>\n<\/tr>\n
107<\/td>\n6.3 Cable
6.4 Cable Assembly
6.4.1 Standard Detachable Cable Assemblies <\/td>\n<\/tr>\n
108<\/td>\nFigure 6-2 \u2013 USB Standard Detachable Cable Assembly <\/td>\n<\/tr>\n
109<\/td>\n6.4.2 High-\/full-speed Captive Cable Assemblies <\/td>\n<\/tr>\n
110<\/td>\nFigure 6-3 \u2013 USB High-\/full-speed Hardwired Cable Assembly <\/td>\n<\/tr>\n
111<\/td>\n6.4.3 Low-speed Captive Cable Assemblies <\/td>\n<\/tr>\n
112<\/td>\nFigure 6-4 \u2013 USB Low-speed Hardwired Cable Assembly <\/td>\n<\/tr>\n
113<\/td>\n6.4.4 Prohibited Cable Assemblies
6.5 Connector Mechanical Configuration and Material Requirements <\/td>\n<\/tr>\n
114<\/td>\n6.5.1 USB Icon Location
6.5.2 USB Connector Termination Data
Figure 6-5 \u2013 USB Icon
Figure 6-6 \u2013 Typical USB Plug Orientation <\/td>\n<\/tr>\n
115<\/td>\n6.5.3 Series \u201cA\u201d and Series \u201cB\u201d Receptacles
Table 6-1 \u2013 USB Connector Termination Assignment <\/td>\n<\/tr>\n
116<\/td>\nFigure 6-7 \u2013 USB Series “A” Receptacle Interface and Mating Drawing <\/td>\n<\/tr>\n
117<\/td>\nFigure 6-8 \u2013 USB Series “B” Receptacle Interface and Mating Drawing <\/td>\n<\/tr>\n
118<\/td>\n6.5.4 Series \u201cA\u201d and Series \u201cB\u201d Plugs <\/td>\n<\/tr>\n
119<\/td>\nFigure 6-9 \u2013 USB Series “A” Plug Interface Drawing <\/td>\n<\/tr>\n
120<\/td>\nFigure 6-10 \u2013 USB Series \u201cB\u201d Plug Interface Drawing <\/td>\n<\/tr>\n
121<\/td>\n6.6 Cable Mechanical Configuration and Material Requirements <\/td>\n<\/tr>\n
122<\/td>\n6.6.1 Description
6.6.2 Construction
Figure 6-11 \u2013 Typical High-\/full-speed Cable Construction <\/td>\n<\/tr>\n
123<\/td>\nTable 6-2 \u2013 Power Pair
Table 6-3 \u2013 Signal Pair <\/td>\n<\/tr>\n
124<\/td>\nTable\u00a06-4 \u2013 Drain Wire Signal Pair <\/td>\n<\/tr>\n
125<\/td>\n6.6.3 Electrical Characteristics
6.6.4 Cable Environmental Characteristics
6.6.5 Listing
Table 6-5 \u2013 Nominal Cable Diameter
Table 6-6 \u2013 Conductor Resistance <\/td>\n<\/tr>\n
126<\/td>\n6.7 Electrical, Mechanical, and Environmental Compliance Standards
Table 6-7 \u2013 USB Electrical, Mechanical, and Environmental Compliance Standards <\/td>\n<\/tr>\n
131<\/td>\n6.7.1 Applicable Documents
6.8 USB Grounding
6.9 PCB Reference Drawings <\/td>\n<\/tr>\n
132<\/td>\nFigure 6-12 \u2013 Single Pin-type Series “A” Receptacle <\/td>\n<\/tr>\n
133<\/td>\nFigure 6-13 \u2013 Dual Pin-type Series “A” Receptacle <\/td>\n<\/tr>\n
134<\/td>\nFigure 6-14 \u2013 Single Pin-type Series “B” Receptacle <\/td>\n<\/tr>\n
135<\/td>\n7 Chapter 7 Electrical
7.1 Signaling
Figure\u00a07-1 \u2013 Example High-speed Capable Transceiver Circuit <\/td>\n<\/tr>\n
137<\/td>\nTable 7-1 \u2013 Description of Functional Elements in the Example Shown in Figure\u00a07-1 <\/td>\n<\/tr>\n
138<\/td>\n7.1.1 USB Driver Characteristics
Figure 7-2 \u2013 Maximum Input Waveforms for USB Signaling <\/td>\n<\/tr>\n
139<\/td>\nFigure 7-3 \u2013 Example Full-speed CMOS Driver Circuit (non High-speed capable) <\/td>\n<\/tr>\n
141<\/td>\nFigure 7-4 \u2013 Full-speed Buffer V\/I Characteristics <\/td>\n<\/tr>\n
142<\/td>\nFigure 7-5 \u2013 Full-speed Buffer V\/I Characteristics for High-speed Capable Transceiver <\/td>\n<\/tr>\n
143<\/td>\nFigure 7-6 \u2013 Full-speed Signal Waveforms
Figure 7-7 \u2013 Low-speed Driver Signal Waveforms <\/td>\n<\/tr>\n
145<\/td>\n7.1.2 Data Signal Rise and Fall, Eye Patterns
Figure\u00a07-8 \u2013 Data Signal Rise and Fall Time <\/td>\n<\/tr>\n
146<\/td>\nFigure 7-9 \u2013 Full-speed Load
Figure 7-10 \u2013 Low-speed Port Loads
Figure 7-11 \u2013 Measurement Planes <\/td>\n<\/tr>\n
147<\/td>\nFigure 7-12 \u2013 Transmitter\/Receiver Test Fixture <\/td>\n<\/tr>\n
148<\/td>\nFigure 7-13 \u2013 Template 1 <\/td>\n<\/tr>\n
149<\/td>\nFigure 7-14 \u2013 Template 2 <\/td>\n<\/tr>\n
150<\/td>\nFigure 7-15 \u2013 Template 3 <\/td>\n<\/tr>\n
151<\/td>\nFigure 7-16 \u2013 Template 4 <\/td>\n<\/tr>\n
152<\/td>\nFigure 7-17 \u2013 Template 5 <\/td>\n<\/tr>\n
153<\/td>\nFigure 7-18 \u2013 Template 6 <\/td>\n<\/tr>\n
154<\/td>\n7.1.3 Cable Skew
7.1.4 Receiver Characteristics <\/td>\n<\/tr>\n
155<\/td>\nFigure 7-19 \u2013 Differential Input Sensitivity Range for Low-\/full-speed <\/td>\n<\/tr>\n
156<\/td>\n7.1.5 Device Speed Identification
Figure 7-20 \u2013 Full-speed Device Cable and Resistor Connections <\/td>\n<\/tr>\n
157<\/td>\n7.1.6 Input Characteristics
Figure 7-21 \u2013 Low-speed Device Cable and Resistor Connections <\/td>\n<\/tr>\n
158<\/td>\nFigure 7-22 \u2013 Placement of Optional Edge Rate Control Capacitors for Low-\/full-speed
Figure 7-23 \u2013 Diagram for High-speed Loading Equivalent Circuit <\/td>\n<\/tr>\n
160<\/td>\n7.1.7 Signaling Levels
Table\u00a07-2 \u2013 Low-\/full-speed Signaling Levels <\/td>\n<\/tr>\n
162<\/td>\nFigure 7-24 \u2013 Upstream Facing Full-speed Port Transceiver
Figure 7-25 \u2013 Downstream Facing Low-\/full-speed Port Transceiver <\/td>\n<\/tr>\n
163<\/td>\nTable 7-3 \u2013 High-speed Signaling Levels <\/td>\n<\/tr>\n
164<\/td>\nTable 7-3 \u2013 High-speed Signaling Levels (Continued) <\/td>\n<\/tr>\n
165<\/td>\nFigure 7-26 \u2013 Low-\/full-speed Disconnect Detection
Figure 7-27 \u2013 Full-\/high-speed Device Connect Detection
Figure 7-28 \u2013 Low-speed Device Connect Detection <\/td>\n<\/tr>\n
166<\/td>\nFigure 7-29 \u2013 Power-on and Connection Events Timing <\/td>\n<\/tr>\n
168<\/td>\nFigure 7-30 \u2013 Low-\/full-speed Packet Voltage Levels <\/td>\n<\/tr>\n
173<\/td>\n7.1.8 Data Encoding\/Decoding
7.1.9 Bit Stuffing
Figure 7-31 \u2013 NRZI Data Encoding <\/td>\n<\/tr>\n
174<\/td>\nFigure 7-32 \u2013 Bit Stuffing
Figure 7-33 \u2013 Illustration of Extra Bit Preceding EOP (Full-\/low-speed) <\/td>\n<\/tr>\n
175<\/td>\n7.1.10 Sync Pattern
Figure 7-34 \u2013 Flow Diagram for Bit Stuffing
Figure 7-35 \u2013 Sync Pattern (Low-\/full-speed) <\/td>\n<\/tr>\n
176<\/td>\n7.1.11 Data Signaling Rate
7.1.12 Frame Interval <\/td>\n<\/tr>\n
177<\/td>\n7.1.13 Data Source Signaling
Figure 7-36 \u2013 Data Jitter Taxonomy <\/td>\n<\/tr>\n
178<\/td>\n7.1.14 Hub Signaling Timings
Figure 7-37 \u2013 SE0 for EOP Width Timing <\/td>\n<\/tr>\n
179<\/td>\nFigure 7-38 \u2013 Hub Propagation Delay of Full-speed Differential Signals <\/td>\n<\/tr>\n
180<\/td>\n7.1.15 Receiver Data Jitter <\/td>\n<\/tr>\n
181<\/td>\nTable 7-4 \u2013 Full-speed Jitter Budget <\/td>\n<\/tr>\n
182<\/td>\n7.1.16 Cable Delay
Table\u00a07-5 \u2013 Low-speed Jitter Budget <\/td>\n<\/tr>\n
183<\/td>\n7.1.17 Cable Attenuation
Figure\u00a07-39 \u2013 Full-speed Cable Delay
Figure 7-40 \u2013 Low-speed Cable Delay <\/td>\n<\/tr>\n
184<\/td>\n7.1.18 Bus Turn-around Time and Inter-packet Delay
Table 7-6 \u2013 Maximum Allowable Cable Loss <\/td>\n<\/tr>\n
185<\/td>\n7.1.19 Maximum End-to-end Signal Delay <\/td>\n<\/tr>\n
186<\/td>\n7.1.20 Test Mode Support
Figure 7-41 \u2013 Worst-case End-to-end Signal Delay Model for Low-\/full-speed <\/td>\n<\/tr>\n
187<\/td>\n7.2 Power Distribution
7.2.1 Classes of Devices <\/td>\n<\/tr>\n
189<\/td>\nFigure\u00a07-42 \u2013 Compound Bus-powered Hub <\/td>\n<\/tr>\n
190<\/td>\nFigure 7-43 \u2013 Compound Self-powered Hub <\/td>\n<\/tr>\n
191<\/td>\nFigure\u00a07-44 \u2013 Low-power Bus-powered Function
Figure 7-45 \u2013 High-power Bus-powered Function <\/td>\n<\/tr>\n
192<\/td>\n7.2.2 Voltage Drop Budget
7.2.3 Power Control During Suspend\/Resume
Figure 7-46 \u2013 Self-powered Function
Figure 7-47 \u2013 Worst-case Voltage Drop Topology (Steady State) <\/td>\n<\/tr>\n
193<\/td>\n7.2.4 Dynamic Attach and Detach
Figure 7-48 \u2013 Typical Suspend Current Averaging Profile <\/td>\n<\/tr>\n
194<\/td>\n7.3 Physical Layer
7.3.1 Regulatory Requirements <\/td>\n<\/tr>\n
195<\/td>\n7.3.2 Bus Timing\/Electrical Characteristics
Table 7-7 \u2013 DC Electrical Characteristics <\/td>\n<\/tr>\n
196<\/td>\nTable 7-7 \u2013 DC Electrical Characteristics (Continued) <\/td>\n<\/tr>\n
197<\/td>\nTable 7-7 \u2013 DC Electrical Characteristics (Continued)
Table 7-8 \u2013 High-speed Source Electrical Characteristics <\/td>\n<\/tr>\n
198<\/td>\nTable 7-9 \u2013 Full-speed Source Electrical Characteristics <\/td>\n<\/tr>\n
199<\/td>\nTable 7-10 \u2013 Low-speed Source Electrical Characteristics <\/td>\n<\/tr>\n
200<\/td>\nTable 7-11 \u2013 Hub\/Repeater Electrical Characteristics <\/td>\n<\/tr>\n
201<\/td>\nTable 7-12 \u2013 Cable Characteristics (Note 14) <\/td>\n<\/tr>\n
202<\/td>\nTable\u00a07-13 \u2013 Hub Event Timings <\/td>\n<\/tr>\n
203<\/td>\nTable 7-13 \u2013 Hub Event Timings (Continued)
Table 7-14 \u2013 Device Event Timings <\/td>\n<\/tr>\n
204<\/td>\nTable 7-14 \u2013 Device Event Timings (Continued) <\/td>\n<\/tr>\n
205<\/td>\n7.3.3 Timing Waveforms
Figure\u00a07-49 \u2013 Differential Data Jitter for Low-\/full-speed
Figure 7-50 \u2013 Differential-to-EOP Transition Skew and EOP Width for Low-\/full-speed
Figure 7-51 \u2013 Receiver Jitter Tolerance for Low-\/full-speed <\/td>\n<\/tr>\n
206<\/td>\nFigure 7-52 \u2013 Hub Differential Delay, Differential Jitter, and SOP Distortion for Low-\/full-speed <\/td>\n<\/tr>\n
207<\/td>\nFigure 7-53 \u2013 Hub EOP Delay and EOP Skew for Low-\/full-speed <\/td>\n<\/tr>\n
208<\/td>\n8 Chapter 8 Protocol Layer
8.1 Byte\/Bit Ordering
8.2 SYNC Field
8.3 Packet Field Formats
8.3.1 Packet Identifier Field
Figure 8-1 \u2013 PID Format <\/td>\n<\/tr>\n
209<\/td>\n8.3.2 Address Fields
Table\u00a08-1 \u2013 PID Types <\/td>\n<\/tr>\n
210<\/td>\n8.3.3 Frame Number Field
8.3.4 Data Field
Figure 8-2 \u2013 ADDR Field
Figure 8-3 \u2013 Endpoint Field <\/td>\n<\/tr>\n
211<\/td>\n8.3.5 Cyclic Redundancy Checks
Figure 8-4 \u2013 Data Field Format <\/td>\n<\/tr>\n
212<\/td>\n8.4 Packet Formats
8.4.1 Token Packets
8.4.2 Split Transaction Special Token Packets
Figure 8-5 \u2013 Token Format <\/td>\n<\/tr>\n
213<\/td>\nFigure 8-6 \u2013 Packets in a Start-split Transaction
Figure 8-7 \u2013 Packets in a Complete-split Transaction <\/td>\n<\/tr>\n
214<\/td>\nFigure 8-8 \u2013 Relationship of Interrupt IN Transaction to High-speed Split Transaction
Figure 8-9 \u2013 Relationship of Interrupt OUT Transaction to High-speed Split OUT Transaction <\/td>\n<\/tr>\n
215<\/td>\nFigure 8-10 \u2013 Start-split (SSPLIT) Token
Figure 8-11 \u2013 Port Field <\/td>\n<\/tr>\n
216<\/td>\nTable\u00a08-2 \u2013 Isochronous OUT Payload Continuation Encoding <\/td>\n<\/tr>\n
217<\/td>\n8.4.3 Start-of-Frame Packets
Figure 8-12 \u2013 Complete-split (CSPLIT) Transaction Token
Figure 8-13 \u2013 SOF Packet
Table 8-3 \u2013 Endpoint Type Values in Split Special Token <\/td>\n<\/tr>\n
218<\/td>\n8.4.4 Data Packets
Figure 8-14 \u2013 Relationship between Frames and Microframes <\/td>\n<\/tr>\n
219<\/td>\n8.4.5 Handshake Packets
Figure 8-15 \u2013 Data Packet Format
Figure 8-16 \u2013 Handshake Packet <\/td>\n<\/tr>\n
220<\/td>\n8.4.6 Handshake Responses
Table 8-4 \u2013 Function Responses to IN Transactions <\/td>\n<\/tr>\n
221<\/td>\n8.5 Transaction Packet Sequences
Table 8-5 \u2013 Host Responses to IN Transactions
Table 8-6 \u2013 Function Responses to OUT Transactions in Order of Precedence <\/td>\n<\/tr>\n
222<\/td>\nFigure 8-17 \u2013 Legend for State Machines <\/td>\n<\/tr>\n
223<\/td>\nFigure 8-18 \u2013 State Machine Context Overview
Figure 8-19 \u2013 Host Controller Top Level Transaction State Machine Hierarchy Overview <\/td>\n<\/tr>\n
224<\/td>\nFigure 8-20 \u2013 Host Controller Non-split Transaction State Machine Hierarchy Overview
Figure 8-21 \u2013 Device Transaction State Machine Hierarchy Overview <\/td>\n<\/tr>\n
225<\/td>\nFigure 8-22 \u2013 Device Top Level State Machine <\/td>\n<\/tr>\n
226<\/td>\nFigure 8-23 \u2013 Device_process_Trans State Machine <\/td>\n<\/tr>\n
227<\/td>\nFigure 8-24 \u2013 Dev_do_OUT State Machine <\/td>\n<\/tr>\n
228<\/td>\nFigure 8-25 \u2013 Dev_do_IN State Machine <\/td>\n<\/tr>\n
229<\/td>\nFigure 8-26 \u2013 HC_Do_nonsplit State Machine <\/td>\n<\/tr>\n
230<\/td>\n8.5.1 NAK Limiting via Ping Flow Control <\/td>\n<\/tr>\n
231<\/td>\nFigure 8-27 \u2013 Host High-speed Bulk OUT\/Control Ping State Machine <\/td>\n<\/tr>\n
232<\/td>\nFigure 8-28 \u2013 Dev_HS_ping State Machine <\/td>\n<\/tr>\n
233<\/td>\nFigure 8-29 \u2013 Device High-speed Bulk OUT \/Control State Machine <\/td>\n<\/tr>\n
234<\/td>\n8.5.2 Bulk Transactions
Figure 8-30 \u2013 Bulk Transaction Format <\/td>\n<\/tr>\n
235<\/td>\nFigure 8-31 \u2013 Bulk\/Control\/Interrupt OUT Transaction Host State Machine <\/td>\n<\/tr>\n
236<\/td>\nFigure 8-32 \u2013 Bulk\/Control\/Interrupt OUT Transaction Device State Machine <\/td>\n<\/tr>\n
237<\/td>\nFigure 8-33 \u2013 Bulk\/Control\/Interrupt IN Transaction Host State Machine <\/td>\n<\/tr>\n
238<\/td>\nFigure 8-34 \u2013 Bulk\/Control\/Interrupt IN Transaction Device State Machine
Figure 8-35 \u2013 Bulk Reads and Writes <\/td>\n<\/tr>\n
239<\/td>\n8.5.3 Control Transfers
Figure 8-36 \u2013 Control SETUP Transaction <\/td>\n<\/tr>\n
240<\/td>\nFigure 8-37 \u2013 Control Read and Write Sequences
Table 8-7 \u2013 Status Stage Responses <\/td>\n<\/tr>\n
242<\/td>\n8.5.4 Interrupt Transactions
8.5.5 Isochronous Transactions
Figure 8-38 \u2013 Interrupt Transaction Format <\/td>\n<\/tr>\n
243<\/td>\nFigure 8-39 \u2013 Isochronous Transaction Format <\/td>\n<\/tr>\n
244<\/td>\nFigure 8-40 \u2013 Isochronous OUT Transaction Host State Machine
Figure 8-41 \u2013 Isochronous OUT Transaction Device State Machine <\/td>\n<\/tr>\n
245<\/td>\nFigure 8-42 \u2013 Isochronous IN Transaction Host State Machine <\/td>\n<\/tr>\n
246<\/td>\n8.6 Data Toggle Synchronization and Retry
Figure 8-43 \u2013 Isochronous IN Transaction Device State Machine <\/td>\n<\/tr>\n
247<\/td>\n8.6.1 Initialization via SETUP Token
8.6.2 Successful Data Transactions
Figure 8-44 \u2013 SETUP Initialization
Figure 8-45 \u2013 Consecutive Transactions <\/td>\n<\/tr>\n
248<\/td>\n8.6.3 Data Corrupted or Not Accepted
8.6.4 Corrupted ACK Handshake
Figure 8-46 \u2013 NAKed Transaction with Retry
Figure 8-47 \u2013 Corrupted ACK Handshake with Retry <\/td>\n<\/tr>\n
249<\/td>\n8.6.5 Low-speed Transactions
Figure 8-48 \u2013 Low-speed Transaction <\/td>\n<\/tr>\n
250<\/td>\n8.7 Error Detection and Recovery
8.7.1 Packet Error Categories
8.7.2 Bus Turn-around Timing
Table 8-8 \u2013 Packet Error Types <\/td>\n<\/tr>\n
251<\/td>\n8.7.3 False EOPs
Figure 8-49 \u2013 Bus Turn-around Timer Usage <\/td>\n<\/tr>\n
252<\/td>\n8.7.4 Babble and Loss of Activity Recovery <\/td>\n<\/tr>\n
253<\/td>\n9 Chapter 9 USB Device Framework
9.1 USB Device States
9.1.1 Visible Device States <\/td>\n<\/tr>\n
254<\/td>\nFigure 9-1 \u2013 Device State Diagram <\/td>\n<\/tr>\n
255<\/td>\nTable 9-1 \u2013 Visible Device States <\/td>\n<\/tr>\n
257<\/td>\n9.1.2 Bus Enumeration
9.2 Generic USB Device Operations <\/td>\n<\/tr>\n
258<\/td>\n9.2.1 Dynamic Attachment and Removal
9.2.2 Address Assignment
9.2.3 Configuration <\/td>\n<\/tr>\n
259<\/td>\n9.2.4 Data Transfer
9.2.5 Power Management
9.2.6 Request Processing <\/td>\n<\/tr>\n
261<\/td>\n9.2.7 Request Error <\/td>\n<\/tr>\n
262<\/td>\n9.3 USB Device Requests
9.3.1 bmRequestType
9.3.2 bRequest
9.3.3 wValue
Table 9-2 \u2013 Format of Setup Data <\/td>\n<\/tr>\n
263<\/td>\n9.3.4 wIndex
9.3.5 wLength
9.4 Standard Device Requests
Figure 9-2 \u2013 wIndex Format when Specifying an Endpoint
Figure 9-3 \u2013 wIndex Format when Specifying an Interface <\/td>\n<\/tr>\n
264<\/td>\nTable 9-3 \u2013 Standard Device Requests
Table 9-4 \u2013 Standard Request Codes <\/td>\n<\/tr>\n
265<\/td>\n9.4.1 Clear Feature
Table 9-5 \u2013 Descriptor Types
Table 9-6 \u2013 Standard Feature Selectors <\/td>\n<\/tr>\n
266<\/td>\n9.4.2 Get Configuration
9.4.3 Get Descriptor <\/td>\n<\/tr>\n
267<\/td>\n9.4.4 Get Interface
9.4.5 Get Status <\/td>\n<\/tr>\n
268<\/td>\nFigure 9-4 \u2013 Information Returned by a GetStatus() Request to a Device
Figure 9-5 \u2013 Information Returned by a GetStatus() Request to an Interface
Figure 9-6 \u2013 Information Returned by a GetStatus() Request to an Endpoint <\/td>\n<\/tr>\n
269<\/td>\n9.4.6 Set Address
9.4.7 Set Configuration <\/td>\n<\/tr>\n
270<\/td>\n9.4.8 Set Descriptor <\/td>\n<\/tr>\n
271<\/td>\n9.4.9 Set Feature
Table 9-7 \u2013 Test Mode Selectors <\/td>\n<\/tr>\n
272<\/td>\n9.4.10 Set Interface
9.4.11 Synch Frame <\/td>\n<\/tr>\n
273<\/td>\n9.5 Descriptors
9.6 Standard USB Descriptor Definitions
9.6.1 Device <\/td>\n<\/tr>\n
274<\/td>\nTable 9-8 \u2013 Standard Device Descriptor <\/td>\n<\/tr>\n
275<\/td>\n9.6.2 Device_Qualifier <\/td>\n<\/tr>\n
276<\/td>\n9.6.3 Configuration
Table 9-9 \u2013 Device_Qualifier Descriptor <\/td>\n<\/tr>\n
277<\/td>\nTable 9-10 \u2013 Standard Configuration Descriptor <\/td>\n<\/tr>\n
278<\/td>\n9.6.4 Other_Speed_Configuration
9.6.5 Interface
Table 9-11 \u2013 Other_Speed_Configuration Descriptor <\/td>\n<\/tr>\n
279<\/td>\n9.6.6 Endpoint
Table 9-12 \u2013 Standard Interface Descriptor <\/td>\n<\/tr>\n
280<\/td>\nTable 9-13 \u2013 Standard Endpoint Descriptor <\/td>\n<\/tr>\n
281<\/td>\nTable 9-13 \u2013 Standard Endpoint Descriptor (Continued) <\/td>\n<\/tr>\n
282<\/td>\n9.6.7 String
Figure 9-7 \u2013 Example of Feedback Endpoint Numbers
Figure 9-8 \u2013 Example of Feedback Endpoint Relationships
Table 9-14 \u2013 Allowed wMaxPacketSize Values for Different Numbers of Transactions per Microframe <\/td>\n<\/tr>\n
283<\/td>\n9.7 Device Class Definitions
9.7.1 Descriptors
9.7.2 Interface(s) and Endpoint Usage
Table 9-15 \u2013 String Descriptor Zero, Specifying Languages Supported by the Device
Table 9-16 \u2013 UNICODE String Descriptor <\/td>\n<\/tr>\n
284<\/td>\n9.7.3 Requests <\/td>\n<\/tr>\n
285<\/td>\n10 Chapter 10 USB Host: Hardware and Software
10.1 Overview of the USB Host
10.1.1 Overview
Figure\u00a010-1 \u2013 Interlayer Communications Model <\/td>\n<\/tr>\n
286<\/td>\nFigure 10-2 \u2013 Host Communications <\/td>\n<\/tr>\n
288<\/td>\n10.1.2 Control Mechanisms
10.1.3 Data Flow <\/td>\n<\/tr>\n
289<\/td>\n10.1.4 Collecting Status and Activity Statistics
10.1.5 Electrical Interface Considerations
10.2 Host Controller Requirements <\/td>\n<\/tr>\n
290<\/td>\n10.2.1 State Handling
10.2.2 Serializer\/Deserializer
10.2.3 Frame and Microframe Generation
Figure 10-3 \u2013 Frame and Microframe Creation <\/td>\n<\/tr>\n
291<\/td>\n10.2.4 Data Processing
10.2.5 Protocol Engine
10.2.6 Transmission Error Handling <\/td>\n<\/tr>\n
292<\/td>\n10.2.7 Remote Wakeup
10.2.8 Root Hub
10.2.9 Host System Interface
10.3 Overview of Software Mechanisms <\/td>\n<\/tr>\n
293<\/td>\n10.3.1 Device Configuration
Figure 10-4 \u2013 Configuration Interactions <\/td>\n<\/tr>\n
295<\/td>\n10.3.2 Resource Management
10.3.3 Data Transfers <\/td>\n<\/tr>\n
296<\/td>\n10.3.4 Common Data Definitions
10.4 Host Controller Driver <\/td>\n<\/tr>\n
297<\/td>\n10.5 Universal Serial Bus Driver
10.5.1 USBD Overview <\/td>\n<\/tr>\n
298<\/td>\nFigure 10-5 \u2013 Universal Serial Bus Driver Structure <\/td>\n<\/tr>\n
299<\/td>\n10.5.2 USBD Command Mechanism Requirements <\/td>\n<\/tr>\n
301<\/td>\n10.5.3 USBD Pipe Mechanisms <\/td>\n<\/tr>\n
303<\/td>\n10.5.4 Managing the USB via the USBD Mechanisms <\/td>\n<\/tr>\n
305<\/td>\n10.5.5 Passing USB Preboot Control to the Operating System
10.6 Operating System Environment Guides <\/td>\n<\/tr>\n
306<\/td>\n11 Chapter 11 Hub Specification
11.1 Overview
11.1.1 Hub Architecture <\/td>\n<\/tr>\n
307<\/td>\n11.1.2 Hub Connectivity
Figure 11-1 \u2013 Hub Architecture <\/td>\n<\/tr>\n
308<\/td>\nFigure 11-2 \u2013 Hub Signaling Connectivity
Figure 11-3 \u2013 Resume Connectivity <\/td>\n<\/tr>\n
309<\/td>\n11.2 Hub Frame\/Microframe Timer
11.2.1 High-speed Microframe Timer Range
11.2.2 Full-speed Frame Timer Range
Table 11-1 \u2013 High-speed Microframe Timer Range Contributions <\/td>\n<\/tr>\n
310<\/td>\n11.2.3 Frame\/Microframe Timer Synchronization
Table 11-2 \u2013 Full-speed Frame Timer Range Contributions <\/td>\n<\/tr>\n
311<\/td>\nFigure 11-4 \u2013 Example High-speed EOF Offsets Due to Propagation Delay Without EOF Advancement
Figure 11-5 \u2013 Example High-speed EOF Offsets Due to Propagation Delay With EOF Advancement <\/td>\n<\/tr>\n
312<\/td>\n11.2.4 Microframe Jitter Related to Frame Jitter
11.2.5 EOF1 and EOF2 Timing Points
Table 11-3 \u2013 Hub and Host EOF1\/EOF2 Timing Points <\/td>\n<\/tr>\n
313<\/td>\nFigure 11-6 \u2013 High-speed EOF2 Timing Point
Figure 11-7 \u2013 High-speed EOF1 Timing Point
Figure 11-8 \u2013 Full-speed EOF Timing Points <\/td>\n<\/tr>\n
315<\/td>\n11.3 Host Behavior at End-of-Frame
11.3.1 Full-\/low-speed Latest Host Packet
11.3.2 Full-\/low-speed Packet Nullification <\/td>\n<\/tr>\n
316<\/td>\n11.3.3 Full-\/low-speed Transaction Completion Prediction
11.4 Internal Port <\/td>\n<\/tr>\n
317<\/td>\n11.4.1 Inactive
11.4.2 Suspend Delay
11.4.3 Full Suspend (Fsus)
11.4.4 Generate Resume (GResume)
Figure\u00a011-9 \u2013 Internal Port State Machine
Table 11-4 \u2013 Internal Port Signal\/Event Definitions <\/td>\n<\/tr>\n
318<\/td>\n11.5 Downstream Facing Ports <\/td>\n<\/tr>\n
319<\/td>\nFigure 11-10 \u2013 Downstream Facing Hub Port State Machine <\/td>\n<\/tr>\n
320<\/td>\n11.5.1 Downstream Facing Port State Descriptions
Table 11-5 \u2013 Downstream Facing Port Signal\/Event Definitions <\/td>\n<\/tr>\n
324<\/td>\n11.5.2 Disconnect Detect Timer <\/td>\n<\/tr>\n
325<\/td>\n11.5.3 Port Indicator <\/td>\n<\/tr>\n
326<\/td>\nFigure 11-11 \u2013 Port Indicator State Diagram
Table 11-6 \u2013 Automatic Port State to Port Indicator Color Mapping <\/td>\n<\/tr>\n
327<\/td>\n11.6 Upstream Facing Port
11.6.1 Full-speed
Table 11-7 \u2013 Port Indicator Color Definitions <\/td>\n<\/tr>\n
328<\/td>\n11.6.2 High-speed
11.6.3 Receiver
Figure 11-12 \u2013 Upstream Facing Port Receiver State Machine <\/td>\n<\/tr>\n
329<\/td>\nTable 11-8 \u2013 Upstream Facing Port Receiver Signal\/Event Definitions <\/td>\n<\/tr>\n
331<\/td>\n11.6.4 Transmitter
Figure 11-13 \u2013 Upstream Facing Port Transmitter State Machine <\/td>\n<\/tr>\n
332<\/td>\nTable 11-9 \u2013 Upstream Facing Port Transmit Signal\/Event Definitions <\/td>\n<\/tr>\n
333<\/td>\n11.7 Hub Repeater
11.7.1 High-speed Packet Connectivity
Figure 11-14 \u2013 Example Hub Repeater Organization <\/td>\n<\/tr>\n
334<\/td>\nFigure 11-15 \u2013 High-speed Port Selector State Machine <\/td>\n<\/tr>\n
335<\/td>\n11.7.2 Hub Repeater State Machine
Table 11-10 \u2013 High-speed Port Selector Signal\/Event Definitions <\/td>\n<\/tr>\n
336<\/td>\nFigure 11-16 \u2013 Hub Repeater State Machine
Table 11-11 \u2013 Hub Repeater Signal\/Event Definitions <\/td>\n<\/tr>\n
337<\/td>\n11.7.3 Wait for Start of Packet from Upstream Port (WFSOPFU)
11.7.4 Wait for End of Packet from Upstream Port (WFEOPFU)
11.7.5 Wait for Start of Packet (WFSOP)
11.7.6 Wait for End of Packet (WFEOP) <\/td>\n<\/tr>\n
338<\/td>\n11.8 Bus State Evaluation
11.8.1 Port Error
11.8.2 Speed Detection <\/td>\n<\/tr>\n
339<\/td>\n11.8.3 Collision
11.8.4 Low-speed Port Behavior <\/td>\n<\/tr>\n
340<\/td>\n11.9 Suspend and Resume <\/td>\n<\/tr>\n
341<\/td>\nFigure 11-17 \u2013 Example Remote-wakeup Resume Signaling With Full-\/low-speed Device
Figure 11-18 \u2013 Example Remote-wakeup Resume Signaling With High-speed Device <\/td>\n<\/tr>\n
342<\/td>\n11.10 Hub Reset Behavior
11.11 Hub Port Power Control <\/td>\n<\/tr>\n
343<\/td>\n11.11.1 Multiple Gangs
11.12 Hub Controller <\/td>\n<\/tr>\n
344<\/td>\n11.12.1 Endpoint Organization
11.12.2 Hub Information Architecture and Operation
Figure 11-19 \u2013 Example Hub Controller Organization <\/td>\n<\/tr>\n
345<\/td>\n11.12.3 Port Change Information Processing
Figure 11-20 \u2013 Relationship of Status, Status Change,and Control Information to Device States <\/td>\n<\/tr>\n
346<\/td>\n11.12.4 Hub and Port Status Change Bitmap
Figure\u00a011-21 \u2013 Port Status Handling Method <\/td>\n<\/tr>\n
347<\/td>\n11.12.5 Over-current Reporting and Recovery
Figure 11-22 \u2013 Hub and Port Status Change Bitmap
Figure\u00a011-23 \u2013 Example Hub and Port Change Bit Sampling <\/td>\n<\/tr>\n
348<\/td>\n11.12.6 Enumeration Handling
11.13 Hub Configuration <\/td>\n<\/tr>\n
349<\/td>\n11.14 Transaction Translator
Table 11-12 \u2013 Hub Power Operating Mode Summary <\/td>\n<\/tr>\n
350<\/td>\n11.14.1 Overview
Figure 11-24 \u2013 Transaction Translator Overview <\/td>\n<\/tr>\n
351<\/td>\nFigure 11-25 \u2013 Periodic and Non-periodic Buffer Sections of TT <\/td>\n<\/tr>\n
352<\/td>\n11.14.2 Transaction Translator Scheduling
Figure 11-26 \u2013 TT Microframe Pipeline for Periodic Split Transactions <\/td>\n<\/tr>\n
353<\/td>\nFigure 11-27 \u2013 TT Nonperiodic Buffering <\/td>\n<\/tr>\n
354<\/td>\n11.15 Split Transaction Notation Information
Figure 11-28 \u2013 Example Full-\/low-speed Handler Scheduling for Start-splits
Figure\u00a011-29 \u2013 Flow Sequence Legend <\/td>\n<\/tr>\n
355<\/td>\nFigure 11-30 \u2013 Legend for State Machines <\/td>\n<\/tr>\n
357<\/td>\n11.16 Common Split Transaction State Machines
Figure\u00a011-31 \u2013 State Machine Context Overview
Figure 11-32 \u2013 Host Controller Split Transaction State Machine Hierarchy Overview <\/td>\n<\/tr>\n
358<\/td>\n11.16.1 Host Controller State Machine
Figure 11-33 \u2013 Transaction Translator State Machine Hierarchy Overview
Figure 11-34 \u2013 Host Controller <\/td>\n<\/tr>\n
359<\/td>\nFigure 11-35 \u2013 HC_Process_Command <\/td>\n<\/tr>\n
360<\/td>\nFigure 11-36 \u2013 HC_Do_Start <\/td>\n<\/tr>\n
361<\/td>\nFigure 11-37 \u2013 HC_Do_Complete <\/td>\n<\/tr>\n
362<\/td>\n11.16.2 Transaction Translator State Machine
Figure 11-38 \u2013 Transaction Translator <\/td>\n<\/tr>\n
363<\/td>\nFigure 11-39 \u2013 TT_Process_Packet <\/td>\n<\/tr>\n
364<\/td>\nFigure 11-40 \u2013 TT_Do_Start <\/td>\n<\/tr>\n
365<\/td>\nFigure 11-41 \u2013 TT_Do_Complete
Figure 11-42 \u2013 TT_BulkSS <\/td>\n<\/tr>\n
366<\/td>\nFigure 11-43 \u2013 TT_BulkCS
Figure 11-44 \u2013 TT_IntSS <\/td>\n<\/tr>\n
367<\/td>\n11.17 Bulk\/Control Transaction Translation Overview
Figure 11-45 \u2013 TT_IntCS
Figure 11-46 \u2013 TT_IsochSS <\/td>\n<\/tr>\n
368<\/td>\n11.17.1 Bulk\/Control Split Transaction Sequences <\/td>\n<\/tr>\n
369<\/td>\nFigure 11-47 \u2013 Sample Algorithm for Compare_buffs <\/td>\n<\/tr>\n
370<\/td>\nFigure 11-48 \u2013 Bulk\/Control OUT Start-split Transaction Sequence <\/td>\n<\/tr>\n
371<\/td>\nFigure 11-49 \u2013 Bulk\/Control OUT Complete-split Transaction Sequence <\/td>\n<\/tr>\n
372<\/td>\nFigure 11-50 \u2013 Bulk\/Control IN Start-split Transaction Sequence <\/td>\n<\/tr>\n
373<\/td>\nFigure 11-51 \u2013 Bulk\/Control IN Complete-split Transaction Sequence <\/td>\n<\/tr>\n
374<\/td>\n11.17.2 Bulk\/Control Split Transaction State Machines
Figure 11-52 \u2013 Bulk\/Control OUT Start-split Transaction Host State Machine <\/td>\n<\/tr>\n
375<\/td>\nFigure 11-53 \u2013 Bulk\/Control OUT Complete-split Transaction Host State Machine <\/td>\n<\/tr>\n
376<\/td>\nFigure 11-54 \u2013 Bulk\/Control OUT Start-split Transaction TT State Machine
Figure 11-55 \u2013 Bulk\/Control OUT Complete-split Transaction TT State Machine <\/td>\n<\/tr>\n
377<\/td>\nFigure 11-56 \u2013 Bulk\/Control IN Start-split Transaction Host State Machine <\/td>\n<\/tr>\n
378<\/td>\nFigure 11-57 \u2013 Bulk\/Control IN Complete-split Transaction Host State Machine <\/td>\n<\/tr>\n
379<\/td>\n11.17.3 Bulk\/Control Sequencing
Figure 11-58 \u2013 Bulk\/Control IN Start-split Transaction TT State Machine
Figure 11-59 \u2013 Bulk\/Control IN Complete-split Transaction TT State Machine <\/td>\n<\/tr>\n
380<\/td>\n11.17.4 Bulk\/Control Buffering Requirements
11.17.5 Other Bulk\/Control Details
11.18 Periodic Split Transaction Pipelining and Buffer Management <\/td>\n<\/tr>\n
381<\/td>\n11.18.1 Best Case Full-Speed Budget
11.18.2 TT Microframe Pipeline
Figure 11-60 \u2013 Best Case Budgeted Full-speed Wire Time With No Bit Stuffing <\/td>\n<\/tr>\n
382<\/td>\n11.18.3 Generation of Full-speed Frames
11.18.4 Host Split Transaction Scheduling Requirements
Figure 11-61 \u2013 Scheduling of TT Microframe Pipeline <\/td>\n<\/tr>\n
383<\/td>\nFigure\u00a011-62 \u2013 Isochronous OUT Example That Avoids a Start-split-end With Zero Data <\/td>\n<\/tr>\n
384<\/td>\nFigure 11-63 \u2013 End of Frame TT Pipeline Scheduling Example
Figure 11-64 \u2013 Isochronous IN Complete-split Schedule Example at L=Y6 <\/td>\n<\/tr>\n
385<\/td>\n11.18.5 TT Response Generation
Figure 11-65 \u2013 Isochronous IN Complete-split Schedule Example at L=Y7 <\/td>\n<\/tr>\n
386<\/td>\n11.18.6 TT Periodic Transaction Handling Requirements <\/td>\n<\/tr>\n
388<\/td>\n11.18.7 TT Transaction Tracking
Figure 11-66 \u2013 Microframe Pipeline <\/td>\n<\/tr>\n
389<\/td>\n11.18.8 TT Complete-split Transaction State Searching
Figure 11-67 \u2013 Advance_Pipeline Pseudocode <\/td>\n<\/tr>\n
390<\/td>\n11.19 Approximate TT Buffer Space Required
11.20 Interrupt Transaction Translation Overview <\/td>\n<\/tr>\n
391<\/td>\n11.20.1 Interrupt Split Transaction Sequences
Figure 11-68 \u2013 Interrupt OUT Start-split Transaction Sequence <\/td>\n<\/tr>\n
392<\/td>\nFigure 11-69 \u2013 Interrupt OUT Complete-split Transaction Sequence
Figure 11-70 \u2013 Interrupt IN Start-split Transaction Sequence <\/td>\n<\/tr>\n
393<\/td>\nFigure 11-71 \u2013 Interrupt IN Complete-split Transaction Sequence <\/td>\n<\/tr>\n
394<\/td>\n11.20.2 Interrupt Split Transaction State Machines
Figure 11-72 \u2013 Interrupt OUT Start-split Transaction Host State Machine <\/td>\n<\/tr>\n
395<\/td>\nFigure 11-73 \u2013 Interrupt OUT Complete-split Transaction Host State Machine <\/td>\n<\/tr>\n
396<\/td>\nFigure 11-74 \u2013 Interrupt OUT Start-split Transaction TT State Machine
Figure 11-75 \u2013 Interrupt OUT Complete-split Transaction TT State Machine <\/td>\n<\/tr>\n
397<\/td>\nFigure 11-76 \u2013 Interrupt IN Start-split Transaction Host State Machine <\/td>\n<\/tr>\n
398<\/td>\nFigure 11-77 \u2013 Interrupt IN Complete-split Transaction Host State Machine <\/td>\n<\/tr>\n
399<\/td>\nFigure 11-78 \u2013 HC_Data_or_Error State Machine
Figure 11-79 \u2013 Interrupt IN Start-split Transaction TT State Machine <\/td>\n<\/tr>\n
400<\/td>\n11.20.3 Interrupt OUT Sequencing
Figure 11-80 \u2013 Interrupt IN Complete-split Transaction TT State Machine <\/td>\n<\/tr>\n
401<\/td>\n11.20.4 Interrupt IN Sequencing
Figure 11-81 \u2013 Example of CRC16 Handling for Interrupt OUT <\/td>\n<\/tr>\n
402<\/td>\n11.21 Isochronous Transaction Translation Overview
Figure 11-82 \u2013 Example of CRC16 Handling for Interrupt IN <\/td>\n<\/tr>\n
403<\/td>\n11.21.1 Isochronous Split Transaction Sequences <\/td>\n<\/tr>\n
404<\/td>\nFigure 11-83 \u2013 Isochronous OUT Start-split Transaction Sequence
Figure 11-84 \u2013 Isochronous IN Start-split Transaction Sequence <\/td>\n<\/tr>\n
405<\/td>\nFigure 11-85 \u2013 Isochronous IN Complete-split Transaction Sequence <\/td>\n<\/tr>\n
406<\/td>\n11.21.2 Isochronous Split Transaction State Machines
Figure 11-86 \u2013 Isochronous OUT Start-split Transaction Host State Machine <\/td>\n<\/tr>\n
407<\/td>\nFigure 11-87 \u2013 Isochronous OUT Start-split Transaction TT State Machine <\/td>\n<\/tr>\n
408<\/td>\nFigure 11-88 \u2013 Isochronous IN Start-split Transaction Host State Machine
Figure 11-89 \u2013 Isochronous IN Complete-split Transaction Host State Machine <\/td>\n<\/tr>\n
409<\/td>\n11.21.3 Isochronous OUT Sequencing
Figure 11-90 \u2013 Isochronous IN Start-split Transaction TT State Machine
Figure 11-91 \u2013 Isochronous IN Complete-split Transaction TT State Machine <\/td>\n<\/tr>\n
410<\/td>\n11.21.4 Isochronous IN Sequencing
Figure 11-92 \u2013 Example of CRC16 Isochronous OUT Data Packet Handling <\/td>\n<\/tr>\n
411<\/td>\n11.22 TT Error Handling
11.22.1 Loss of TT Synchronization With HS SOFs
Figure 11-93 \u2013 Example of CRC16 Isochronous IN Data Packet Handling <\/td>\n<\/tr>\n
412<\/td>\n11.22.2 TT Frame and Microframe Timer Synchronization Requirements <\/td>\n<\/tr>\n
413<\/td>\n11.23 Descriptors
Figure 11-94 \u2013 Example Frame\/Microframe Synchronization Events <\/td>\n<\/tr>\n
414<\/td>\n11.23.1 Standard Descriptors for Hub Class <\/td>\n<\/tr>\n
422<\/td>\n11.23.2 Class-specific Descriptors
Table 11-13 \u2013 Hub Descriptor <\/td>\n<\/tr>\n
423<\/td>\n11.24 Requests
11.24.1 Standard Requests
Table 11-14 \u2013 Hub Responses to Standard Device Requests <\/td>\n<\/tr>\n
424<\/td>\n11.24.2 Class-specific Requests
Table 11-15 \u2013 Hub Class Requests <\/td>\n<\/tr>\n
425<\/td>\nTable 11-16 \u2013 Hub Class Request Codes
Table 11-17 \u2013 Hub Class Feature Selectors <\/td>\n<\/tr>\n
427<\/td>\nTable 11-18 \u2013 wValue Field for Clear_TT_Buffer <\/td>\n<\/tr>\n
428<\/td>\nTable 11-19 \u2013 Hub Status Field, wHubStatus <\/td>\n<\/tr>\n
429<\/td>\nTable 11-20 \u2013 Hub Change Field, wHubChange <\/td>\n<\/tr>\n
430<\/td>\nTable 11-21 \u2013 Port Status Field, wPortStatus <\/td>\n<\/tr>\n
434<\/td>\nTable 11-22 \u2013 Port Change Field, wPortChange <\/td>\n<\/tr>\n
435<\/td>\nTable 11-23 \u2013 Format of Returned TT State <\/td>\n<\/tr>\n
439<\/td>\nTable 11-24 \u2013 Test Mode Selector Codes
Table 11-25 \u2013 Port Indicator Selector Codes <\/td>\n<\/tr>\n
440<\/td>\nAppendix A Transaction Examples
A.1 Bulk\/Control OUT and SETUP Transaction Examples <\/td>\n<\/tr>\n
441<\/td>\nFigure A-1 \u2013 Normal No Smash <\/td>\n<\/tr>\n
442<\/td>\nFigure A-2 \u2013 Normal HS DATA0\/1 Smash <\/td>\n<\/tr>\n
443<\/td>\nFigure A-3 \u2013 Normal HS DATA0\/1 3 Strikes Smash <\/td>\n<\/tr>\n
444<\/td>\nFigure A-4 \u2013 Normal HS ACK(S) Smash (case 1) <\/td>\n<\/tr>\n
445<\/td>\nFigure A-5 \u2013 Normal HS ACK(S) Smash (case 2) <\/td>\n<\/tr>\n
446<\/td>\nFigure A-6 \u2013 Normal HS ACK(S) 3 Strikes Smash <\/td>\n<\/tr>\n
447<\/td>\nFigure A-7 \u2013 Normal HS CSPLIT Smash <\/td>\n<\/tr>\n
448<\/td>\nFigure A-8 \u2013 Normal HS CSPLIT 3 Strikes Smash <\/td>\n<\/tr>\n
449<\/td>\nFigure A-9 \u2013 Normal HS ACK(C) Smash <\/td>\n<\/tr>\n
450<\/td>\nFigure A-10 \u2013 Normal S ACK(C) 3 Strikes Smash <\/td>\n<\/tr>\n
451<\/td>\nFigure A-11 \u2013 Normal FS\/LS DATA0\/1 Smash <\/td>\n<\/tr>\n
452<\/td>\nFigure A-12 \u2013 Normal FS\/LS DATA0\/1 3 Strikes Smash <\/td>\n<\/tr>\n
453<\/td>\nFigure A-13 \u2013 Normal FS\/LS ACK Smash <\/td>\n<\/tr>\n
454<\/td>\nFigure A-14 \u2013 Normal FS\/LS ACK 3 Strikes Smash <\/td>\n<\/tr>\n
455<\/td>\nFigure A-15 \u2013 No buffer Available No Smash (HS NAK(S)) <\/td>\n<\/tr>\n
456<\/td>\nFigure A-16 \u2013 No Buffer Available HS NAK(S) Smash <\/td>\n<\/tr>\n
457<\/td>\nFigure A-17 \u2013 No Buffer Available HS NAK(S) 3 Strikes Smash <\/td>\n<\/tr>\n
458<\/td>\nFigure A-18 \u2013 CS Earlier No Smash (HS NYET) <\/td>\n<\/tr>\n
459<\/td>\nFigure A-19 \u2013 CS Earlier HS NYET Smash (case 1) <\/td>\n<\/tr>\n
460<\/td>\nFigure A-20 \u2013 CS Earlier HS NYET Smash (case 2) <\/td>\n<\/tr>\n
461<\/td>\nFigure A-21 \u2013 CS Earlier HS NYET 3 Strikes Smash <\/td>\n<\/tr>\n
462<\/td>\nFigure A-22 \u2013 Device Busy No Smash(FS\/LS NAK) <\/td>\n<\/tr>\n
463<\/td>\nFigure A-23 \u2013 Device Stall No Smash(FS\/LS STALL) <\/td>\n<\/tr>\n
464<\/td>\nA.2 Bulk\/Control IN Transaction Examples <\/td>\n<\/tr>\n
465<\/td>\nFigure A-24 \u2013 Normal No Smash <\/td>\n<\/tr>\n
466<\/td>\nFigure A-25 \u2013 Normal HS SSPLIT Smash <\/td>\n<\/tr>\n
467<\/td>\nFigure A-26 \u2013 Normal SSPLIT 3 Strikes Smash <\/td>\n<\/tr>\n
468<\/td>\nFigure A-27 \u2013 Normal HS ACK(S) Smash (case 1) <\/td>\n<\/tr>\n
469<\/td>\nFigure A-28 \u2013 Normal HS ACK(S) Smash (case 2) <\/td>\n<\/tr>\n
470<\/td>\nFigure A-29 \u2013 Normal HS ACK(S) 3 Strikes Smash <\/td>\n<\/tr>\n
471<\/td>\nFigure A-30 \u2013 Normal HS CSPLIT Smash <\/td>\n<\/tr>\n
472<\/td>\nFigure A-31 \u2013 Normal HS CSPLIT 3 Strikes Smash <\/td>\n<\/tr>\n
473<\/td>\nFigure A-32 \u2013 Normal HS DATA0\/1 Smash <\/td>\n<\/tr>\n
474<\/td>\nFigure A-33 \u2013 Normal HS DATA0\/1 3 Strikes Smash <\/td>\n<\/tr>\n
475<\/td>\nFigure A-34 \u2013 Normal FS\/LS IN Smash <\/td>\n<\/tr>\n
476<\/td>\nFigure A-35 \u2013 Normal FS\/LS IN 3 Strikes Smash <\/td>\n<\/tr>\n
477<\/td>\nFigure A-36 \u2013 Normal FS\/LS DATA0\/1 Smash <\/td>\n<\/tr>\n
478<\/td>\nFigure A-37 \u2013 Normal FS\/LS DATA0\/1 3 Strikes Smash <\/td>\n<\/tr>\n
479<\/td>\nFigure A-38 \u2013 Normal FS\/LS ACK Smash <\/td>\n<\/tr>\n
480<\/td>\nFigure A-39 \u2013 No Buffer Available No Smash(HS NAK(S)) <\/td>\n<\/tr>\n
481<\/td>\nFigure A-40 \u2013 No Buffer Available HS NAK(S) Smash <\/td>\n<\/tr>\n
482<\/td>\nFigure A-41 \u2013 No Buffer Available HS NAK(S) 3 Strikes Smash <\/td>\n<\/tr>\n
483<\/td>\nFigure A-42 \u2013 CS Earlier No Smash (HS NYET) <\/td>\n<\/tr>\n
484<\/td>\nFigure A-43 \u2013 CS Earlier HS NYET Smash (case 1) <\/td>\n<\/tr>\n
485<\/td>\nFigure A-44 \u2013 CS Earlier HS NYET Smash (case 2) <\/td>\n<\/tr>\n
486<\/td>\nFigure A-45 \u2013 Device Busy No Smash(FS\/LS NAK) <\/td>\n<\/tr>\n
487<\/td>\nFigure A-46 \u2013 Device Stall No Smash(FS\/LS STALL) <\/td>\n<\/tr>\n
488<\/td>\nA.3 Interrupt OUT Transaction Examples <\/td>\n<\/tr>\n
490<\/td>\nFigure A-47 \u2013 Normal No Smash(FS\/LS Handshake Packet is Done by M+1) <\/td>\n<\/tr>\n
491<\/td>\nFigure A-48 \u2013 Normal HS DATA0\/1 Smash <\/td>\n<\/tr>\n
492<\/td>\nFigure A-49 \u2013 Normal HS CSPLIT Smash <\/td>\n<\/tr>\n
493<\/td>\nFigure A-50 \u2013 Normal HS CSPLIT 3 Strikes Smash <\/td>\n<\/tr>\n
494<\/td>\nFigure A-51 \u2013 Normal HS ACK(C) Smash <\/td>\n<\/tr>\n
495<\/td>\nFigure A-52 \u2013 Normal HS ACK(C) 3 Strikes Smash <\/td>\n<\/tr>\n
496<\/td>\nFigure A-53 \u2013 Normal FS\/LS DATA0\/1 Smash <\/td>\n<\/tr>\n
497<\/td>\nFigure A-54 \u2013 Normal FS\/LS ACK Smash <\/td>\n<\/tr>\n
498<\/td>\nFigure A-55 \u2013 Searching No Smash <\/td>\n<\/tr>\n
499<\/td>\nFigure A-56 \u2013 CS Earlier No Smash(HS NYET and FS\/LS Handshake Packet is Done by M+2) <\/td>\n<\/tr>\n
500<\/td>\nFigure A-57 \u2013 CS Earlier No Smash(HS NYET and FS\/LS Handshake Packet is Done by M+3) <\/td>\n<\/tr>\n
501<\/td>\nFigure A-58 \u2013 CS Earlier HS NYET Smash <\/td>\n<\/tr>\n
502<\/td>\nFigure A-59 \u2013 CS Earlier HS NYET 3 Strikes Smash <\/td>\n<\/tr>\n
503<\/td>\nFigure A-60 \u2013 Abort and Free Abort(FS\/LS Transaction is Continued at End of M+3) <\/td>\n<\/tr>\n
504<\/td>\nFigure A-61 \u2013 Abort and Free Free(FS\/LS Transaction is not Started at End of M+3) <\/td>\n<\/tr>\n
505<\/td>\nFigure A-62 \u2013 Device Busy No Smash(FS\/LS NAK) <\/td>\n<\/tr>\n
506<\/td>\nFigure A-63 \u2013 Device Stall No Smash(FS\/LS STALL) <\/td>\n<\/tr>\n
507<\/td>\nA.4 Interrupt IN Transaction Examples <\/td>\n<\/tr>\n
509<\/td>\nFigure A-64 \u2013 Normal No Smash (FS\/LS Data Packet is on M+1) <\/td>\n<\/tr>\n
510<\/td>\nFigure A-65 \u2013 Normal HS SSPLIT Smash <\/td>\n<\/tr>\n
511<\/td>\nFigure A-66 \u2013 Normal HS CSPLIT Smash <\/td>\n<\/tr>\n
512<\/td>\nFigure A-67 \u2013 Normal HS CSPLIT 3 Strikes Smash <\/td>\n<\/tr>\n
513<\/td>\nFigure A-68 \u2013 Normal HS DATA0\/1 Smash <\/td>\n<\/tr>\n
514<\/td>\nFigure A-69 \u2013 Normal HS DATA0\/1 3 Strikes Smash <\/td>\n<\/tr>\n
515<\/td>\nFigure A-70 \u2013 Normal FS\/LS IN Smash <\/td>\n<\/tr>\n
516<\/td>\nFigure A-71 \u2013 Normal FS\/LS DATA0\/1 Smash <\/td>\n<\/tr>\n
517<\/td>\nFigure A-72 \u2013 Normal FS\/LS ACK Smash <\/td>\n<\/tr>\n
518<\/td>\nFigure A-73 \u2013 Searching No Smash <\/td>\n<\/tr>\n
519<\/td>\nFigure A-74 \u2013 CS Earlier No Smash (HS MDATA and FS\/LS Data Packet is on M+1 and M+2) <\/td>\n<\/tr>\n
520<\/td>\nFigure A-75 \u2013 CS Earlier No Smash (HS NYET and FS\/LS Data Packet is on M+2) <\/td>\n<\/tr>\n
521<\/td>\nFigure A-76 \u2013 CS Earlier No Smash (HS NYET and MDATA and FS\/LS Data Packet is on M+2 and M+3) <\/td>\n<\/tr>\n
522<\/td>\nFigure A-77 \u2013 CS Earlier No Smash(HS NYET and FS\/LS Data Packet is on M+3) <\/td>\n<\/tr>\n
523<\/td>\nFigure A-78 \u2013 CS Earlier HS NYET Smash <\/td>\n<\/tr>\n
524<\/td>\nFigure A-79 \u2013 CS Earlier HS NYET 3 Strikes Smash <\/td>\n<\/tr>\n
525<\/td>\nFigure A-80 \u2013 Abort and Free Abort (HS NYET and FS\/LS Transaction is Continued at End of M+3) <\/td>\n<\/tr>\n
526<\/td>\nFigure A-81 \u2013 Abort and Free Free (HS NYET and FS\/LS Transaction is not Started at End of M+3) <\/td>\n<\/tr>\n
527<\/td>\nFigure A-82 \u2013 Device Busy No Smash(FS\/LS NAK) <\/td>\n<\/tr>\n
528<\/td>\nFigure A-83 \u2013 Device Stall No Smash(FS\/LS STALL) <\/td>\n<\/tr>\n
529<\/td>\nA.5 Isochronous OUT Split-transaction Examples <\/td>\n<\/tr>\n
538<\/td>\nA.6 Isochronous IN Split-transaction Examples <\/td>\n<\/tr>\n
552<\/td>\nAppendix B Example Declarations for State Machines <\/td>\n<\/tr>\n
553<\/td>\nB.1 Global Declarations <\/td>\n<\/tr>\n
556<\/td>\nB.2 Host Controller Declarations <\/td>\n<\/tr>\n
558<\/td>\nB.3 Transaction Translator Declarations <\/td>\n<\/tr>\n
562<\/td>\nAppendix C Reset Protocol State Diagrams
C.1 Downstream Facing Port State Diagram <\/td>\n<\/tr>\n
563<\/td>\nFigure C-1 \u2013 Downstream Facing Port Reset Protocol State Diagram <\/td>\n<\/tr>\n
564<\/td>\nC.2 Upstream Facing Port State Diagram
C.2.1 Reset From Suspended State <\/td>\n<\/tr>\n
565<\/td>\nFigure C-2 \u2013 Upstream Facing Port Reset Detection State Diagram <\/td>\n<\/tr>\n
566<\/td>\nFigure C-3 \u2013 Upstream Facing Port Reset Handshake State Diagram <\/td>\n<\/tr>\n
567<\/td>\nC.2.2 Reset From Full-speed Non-suspended State
C.2.3 Reset From High-speed Non-suspended State
C.2.4 Reset Handshake <\/td>\n<\/tr>\n
639<\/td>\nTable 5-3 \u2013 High-speed Control Transfer Limits <\/td>\n<\/tr>\n
640<\/td>\nTable 5-8 \u2013 High-speed Interrupt Transaction Limits <\/td>\n<\/tr>\n
641<\/td>\nTable 5-5 \u2013 High-speed Isochronous Transaction Limits <\/td>\n<\/tr>\n
646<\/td>\nFigure 8-27 \u2013 Host High-speed Bulk OUT\/Control Ping State Machine <\/td>\n<\/tr>\n
647<\/td>\nFigure 8-31 \u2013 FS Bulk, FS\/LS\/ Control, or HS\/FS\/LS Interrupt\/ OUT Transaction Host State Machine <\/td>\n<\/tr>\n
648<\/td>\nFigure 8-32 \u2013 FS Bulk, \/FS\/LS Control, \/or HS\/FS\/LSInterrupt OUT Transaction Host State Machine <\/td>\n<\/tr>\n
650<\/td>\nTable 9-3 \u2013 Standard Device Requests <\/td>\n<\/tr>\n
664<\/td>\nFigure11-11 \u2013 Port Indicator State Diagram <\/td>\n<\/tr>\n
666<\/td>\nTable 11-14 \u2013 Hub Responses to Standard Device Requests <\/td>\n<\/tr>\n
668<\/td>\nTable 11-21 \u2013 Port Status Field, wPortStatus <\/td>\n<\/tr>\n
673<\/td>\nFigure 6-1 \u2013 Keyed Connector Protocol <\/td>\n<\/tr>\n
675<\/td>\nFigure 6-2 \u2013 USB Standard Detachable Cable Assembly <\/td>\n<\/tr>\n
676<\/td>\nFigure 6-3 \u2013 USB Standard Mini-connector Detachable Cable Assembly <\/td>\n<\/tr>\n
678<\/td>\nFigure 6-3 \u2013 USB High-\/full-speed Hardwired Cable Assembly <\/td>\n<\/tr>\n
680<\/td>\nFigure 6-46-5 \u2013 USB Low-speed Hardwired Cable Assembly <\/td>\n<\/tr>\n
682<\/td>\nFigure 6-56-6 \u2013 USB Icon <\/td>\n<\/tr>\n
683<\/td>\nFigure 6-66-7 \u2013 Typical USB Plug Orientation <\/td>\n<\/tr>\n
684<\/td>\nFigure 6-8 \u2013 Typical USB \u201cMini-B\u201d Connector Plug Orientation <\/td>\n<\/tr>\n
685<\/td>\nTable 6-1 \u2013 USB Series \u201cA\u201d and Series \u201cB\u201d Connector Termination Assignment
Table 6-2 \u2013 USB Series \u201cmini-B\u201d Connector Termination Assignment <\/td>\n<\/tr>\n
686<\/td>\nFigure 6-76-9 \u2013 USB Series “A” Receptacle Interface and Mating Drawing <\/td>\n<\/tr>\n
687<\/td>\nFigure 6-86-10 \u2013 USB Series “B” Receptacle Interface and Mating Drawing <\/td>\n<\/tr>\n
688<\/td>\nFigure 6-11 \u2013 USB Series “Mini-B” Receptacle Interface and Mating Drawing <\/td>\n<\/tr>\n
689<\/td>\nFigure 6-12 \u2013 USB Series \u201cMini-B\u201d Receptacle Interface Drawing (Detail).tiff <\/td>\n<\/tr>\n
692<\/td>\nFigure 6-96-13 \u2013 USB Series “A” Plug Interface Drawing <\/td>\n<\/tr>\n
693<\/td>\nFigure 6-106-14 \u2013 USB Series \u201cB\u201d Plug Interface Drawing <\/td>\n<\/tr>\n
694<\/td>\nFigure 6-15 \u2013 USB Series \u201cMini-B\u201d Plug Interface Drawing <\/td>\n<\/tr>\n
697<\/td>\nFigure 6-116-16 \u2013 Typical High-\/full-speed Cable Construction <\/td>\n<\/tr>\n
698<\/td>\nTable 6-26-3 \u2013 Power Pair
Table 6-36-4 \u2013 Signal Pair <\/td>\n<\/tr>\n
699<\/td>\nTable\u00a06-46-5 \u2013 Drain Wire Signal Pair <\/td>\n<\/tr>\n
700<\/td>\nTable 6-56-6 \u2013 Nominal Cable Diameter
Table 6-66-7 \u2013 Conductor Resistance <\/td>\n<\/tr>\n
701<\/td>\nTable 6-76-8 \u2013 USB Electrical, Mechanical, and Environmental Compliance Standards <\/td>\n<\/tr>\n
702<\/td>\nTable 6-76-8 \u2013 USB Electrical, Mechanical, and Environmental Compliance Standards (Continued) <\/td>\n<\/tr>\n
703<\/td>\nTable 6-76-8 \u2013 USB Electrical, Mechanical, and Environmental Compliance Standards (Continued) <\/td>\n<\/tr>\n
704<\/td>\nTable 6-76-8\u2013 USB Electrical, Mechanical, and Environmental Compliance Standards (Continued) <\/td>\n<\/tr>\n
705<\/td>\nTable 6-76-8\u2013 USB Electrical, Mechanical, and Environmental Compliance Standards (Continued) <\/td>\n<\/tr>\n
707<\/td>\nFigure 6-126-17 \u2013 Single Pin-type Series “A” Receptacle <\/td>\n<\/tr>\n
708<\/td>\nFigure 6-136-18 \u2013 Dual Pin-type Series “A” Receptacle <\/td>\n<\/tr>\n
709<\/td>\nFigure 6-146-19 \u2013 Single Pin-type Series “B” Receptacle <\/td>\n<\/tr>\n
710<\/td>\nFigure 6-20 \u2013 Single Pin-Type Series \u201cMini-B\u201d Receptacle <\/td>\n<\/tr>\n
720<\/td>\nTable 9-13 \u2013 Standard Endpoint Descriptor (Continued) <\/td>\n<\/tr>\n
722<\/td>\nTable 11-6 \u2013 Automatic Port State to Port Indicator Color Mapping <\/td>\n<\/tr>\n
723<\/td>\nFigure 11-11 \u2013 Port Indicator State Diagram <\/td>\n<\/tr>\n
728<\/td>\nFigure 11-82 \u2013 Example of CRC16 Handling for Interrupt IN
Figure 11-93 \u2013 Example of CRC16 Isochronous IN Data Packet Handling <\/td>\n<\/tr>\n
736<\/td>\nTable 9-5 \u2013 Descriptor Types <\/td>\n<\/tr>\n
737<\/td>\nTable 9-13 \u2013 Standard Interface Association Descriptor
Table 9-1314 \u2013 Standard Endpoint Descriptor <\/td>\n<\/tr>\n
739<\/td>\nFigure 6-15 \u2013 USB Series \u201cMini-B\u201d Plug Interface Drawing (1 of 2) <\/td>\n<\/tr>\n
740<\/td>\nFigure 6-15 \u2013 USB Series \u201cMini-B\u201d Plug Interface Drawing (2 of 2) <\/td>\n<\/tr>\n
743<\/td>\nTable 9-16 \u2013 UNICODE String Descriptor <\/td>\n<\/tr>\n
746<\/td>\nTable 1-1 \u2013 USB Link Power Management (Lx) States <\/td>\n<\/tr>\n
747<\/td>\nFigure 1-1 \u2013 LPM State Transition Diagram
Table 1-2 \u2013 Summary Similarities\/Differences Between L1 and L2 <\/td>\n<\/tr>\n
748<\/td>\nTable 2-1 \u2013 PID Types <\/td>\n<\/tr>\n
749<\/td>\nFigure 2-1 \u2013 Packets in an Extension Token Transaction <\/td>\n<\/tr>\n
750<\/td>\nFigure 2-2 \u2013 LPM Extended Token
Table 2-2 \u2013 SubPID Types
Table 2-2 \u2013 SubPID Types (cont.) <\/td>\n<\/tr>\n
751<\/td>\nFigure 2-3 \u2013 LPM Transaction Format
Table 2-3 \u2013 LPM Token bmAttributes Field Definition <\/td>\n<\/tr>\n
752<\/td>\nTable 3-1 \u2013 USB Device Capabilities \u2013 USB 2.0 Extension Descriptor <\/td>\n<\/tr>\n
753<\/td>\nTable 3-1 \u2013 USB Device Capabilities \u2013 USB 2.0 Extension Descriptor (cont.) <\/td>\n<\/tr>\n
754<\/td>\nFigure\u00a04-1 \u2013 Port Control Model for Transitioning a Port to L1 <\/td>\n<\/tr>\n
755<\/td>\nFigure 4-2 \u2013 LPM Transaction and Transition Timing to L1 <\/td>\n<\/tr>\n
756<\/td>\nFigure 4-3 \u2013 Device Initiated L1 to L0 Transition (Remote Wake) <\/td>\n<\/tr>\n
757<\/td>\nFigure 4-4 \u2013 Example Remote-wakeup L1 Exit with Full-speed DeviceUnder Connected Hub <\/td>\n<\/tr>\n
759<\/td>\nTable 4-1 \u2013 Device Initiated Resume Propagation and Adjacent Port Side-effects <\/td>\n<\/tr>\n
760<\/td>\nFigure 4-5 \u2013 Basic Port Control Model for Transitioning a Port out of L1
Figure 4-6 \u2013 Host Initiated L1 to L0 Transition (L1 Exit) <\/td>\n<\/tr>\n
761<\/td>\nFigure 4-7 \u2013 USB 2.0 Hub Reference Port State Machine Relationships with L1 Additions <\/td>\n<\/tr>\n
762<\/td>\nFigure 4-8 \u2013 L1 Addendum to the Upstream Facing Port Receiver State Machine
Table 4-2 \u2013 Upstream Facing Port Receiver Signal\/Event Definitions (Addendum) <\/td>\n<\/tr>\n
764<\/td>\nFigure 4-9 \u2013 Addendum to the Upstream Facing Port Transmitter State Machine
Table 4-3 \u2013 Upstream Facing Port Transmitter Signal\/Event Definitions (Addendum) <\/td>\n<\/tr>\n
765<\/td>\nFigure 4-10 \u2013 Addendum to the Internal Port State Machine <\/td>\n<\/tr>\n
766<\/td>\nTable 4-4 \u2013 Internal Port Signal\/Event Definitions (Addendum) <\/td>\n<\/tr>\n
767<\/td>\nFigure 4-11 \u2013 Addendum to Downstream Facing Hub Port State Machine
Table 4-5 \u2013 Downstream Port Signal\/Event Definitions (Addendum) <\/td>\n<\/tr>\n
770<\/td>\nTable 4-6 \u2013 Summary LPM Timing Characteristics
Table 4-7 \u2013 Hub Class Feature Selectors <\/td>\n<\/tr>\n
771<\/td>\nTable 4-7 \u2013 Hub Class Feature Selectors (cont.)
Table 4-8 \u2013 wIndex Definition for Clear Port Feature on an LPM Enabled Hub <\/td>\n<\/tr>\n
772<\/td>\nTable 4-9 \u2013 Port Status Bits with L1 Additions <\/td>\n<\/tr>\n
773<\/td>\nTable 4-10 \u2013 Port Change Bits with L1 Additions <\/td>\n<\/tr>\n
774<\/td>\nTable 4-11 \u2013 Set and Test Port Feature Details <\/td>\n<\/tr>\n
789<\/td>\nFigure 7-29 \u2013 Connect Event Timing <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":"

Universal Serial Bus interfaces for data and power – Universal Serial Bus Specification, Revision 2.0 (TA 14)<\/b><\/p>\n\n\n\n\n
Published By<\/td>\nPublication Date<\/td>\nNumber of Pages<\/td>\n<\/tr>\n
BSI<\/b><\/a><\/td>\n2016<\/td>\n796<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n","protected":false},"featured_media":229006,"template":"","meta":{"rank_math_lock_modified_date":false,"ep_exclude_from_search":false},"product_cat":[631,2641],"product_tag":[],"class_list":{"0":"post-229005","1":"product","2":"type-product","3":"status-publish","4":"has-post-thumbnail","6":"product_cat-33-120-20","7":"product_cat-bsi","9":"first","10":"instock","11":"sold-individually","12":"shipping-taxable","13":"purchasable","14":"product-type-simple"},"_links":{"self":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product\/229005","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product"}],"about":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/types\/product"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media\/229006"}],"wp:attachment":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media?parent=229005"}],"wp:term":[{"taxonomy":"product_cat","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_cat?post=229005"},{"taxonomy":"product_tag","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_tag?post=229005"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}