{"id":125387,"date":"2024-10-19T05:07:09","date_gmt":"2024-10-19T05:07:09","guid":{"rendered":"https:\/\/pdfstandards.shop\/product\/uncategorized\/ieee-1149-7-2022-3\/"},"modified":"2024-10-24T23:15:09","modified_gmt":"2024-10-24T23:15:09","slug":"ieee-1149-7-2022-3","status":"publish","type":"product","link":"https:\/\/pdfstandards.shop\/product\/publishers\/ieee\/ieee-1149-7-2022-3\/","title":{"rendered":"IEEE 1149.7-2022"},"content":{"rendered":"

Revision Standard – Active. Circuitry that may be added to an integrated circuit to provide access to on-chip Test Access Ports (TAPs) specified by IEEE Std 1149.1 is described in this standard. The circuitry uses IEEE Std 1149.1 as its foundation, providing complete backward compatibility, while aggressively adding features to support test and applications debug. It defines six classes of IEEE 1149.7 Test Access Ports (TAP.7s), T0 to T5, with each class providing incremental capability, building on that of the lower level classes. Class T0 provides the behavior specified by 1149.1 from startup when there are multiple on-chip TAPs. Class T1 adds common debug functions and features to minimize power consumption. Class T2 adds operating modes that maximize scan performance. It also provides an optional hot-connection capability to prevent system corruption when a connection is made to a powered system. Class T3 supports operation in either a four-wire Series or Star Scan Topology. Class T4 provides for communication with either a two-pin or four-pin interface. The two-pin operation serializes IEEE 1149.1 transactions and provides for higher Test Clock rates. Class T5 adds the ability to perform data transfers concurrently with scan, supports utilization of functions other than scan, and provides control of TAP.7 pins to custom debug technologies in a manner that ensures current and future interoperability.<\/p>\n

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PDF Pages<\/th>\nPDF Title<\/th>\n<\/tr>\n
1<\/td>\nIEEE Std 1149.7-2022 Front Cover <\/td>\n<\/tr>\n
2<\/td>\nTitle page <\/td>\n<\/tr>\n
4<\/td>\nNotice and Disclaimer of Liability Concerning the Use of IEEE Standards Documents
Translations <\/td>\n<\/tr>\n
5<\/td>\nOfficial statements
Comments on standards
Laws and regulations
Data privacy
Copyrights <\/td>\n<\/tr>\n
6<\/td>\nPhotocopies
Updating of IEEE Standards documents
Errata
Patents <\/td>\n<\/tr>\n
7<\/td>\nIMPORTANT NOTICE <\/td>\n<\/tr>\n
8<\/td>\nParticipants <\/td>\n<\/tr>\n
9<\/td>\nIntroduction
History of the development of this standard <\/td>\n<\/tr>\n
10<\/td>\nChanges introduced by this revision <\/td>\n<\/tr>\n
11<\/td>\nContents <\/td>\n<\/tr>\n
40<\/td>\nFigures <\/td>\n<\/tr>\n
51<\/td>\nTables <\/td>\n<\/tr>\n
57<\/td>\n1. Overview
1.1 Scope
1.2 Purpose
1.3 Word usage <\/td>\n<\/tr>\n
58<\/td>\n1.4 Contrasting IEEE Std 1149.1 and this standard <\/td>\n<\/tr>\n
59<\/td>\n1.5 Challenges <\/td>\n<\/tr>\n
60<\/td>\n1.6 Important considerations
1.7 Nomenclature
1.7.1 References to technology and standards
1.7.2 Describing Test Access Port behaviors <\/td>\n<\/tr>\n
61<\/td>\n1.7.3 Describing TAPs and TAP controllers <\/td>\n<\/tr>\n
62<\/td>\n1.7.4 Describing scan exchanges
1.7.5 Describing TAP signals <\/td>\n<\/tr>\n
63<\/td>\n1.8 Ensuring transparency to IEEE 1149.1 intellectual property
1.8.1 IEEE 1149.1 constraints
1.8.2 IEEE 1149.1 constraints\/requirements balancing
1.8.3 IEEE 1149.1 upgrade path <\/td>\n<\/tr>\n
64<\/td>\n1.9 Maximizing compatibility with 1149.1 IP
1.9.1 IEEE 1149.1 infrastructure
1.9.1.1 IEEE 1149.1 instructions
1.9.1.2 IEEE 1149.1 Scan Paths
1.9.1.3 IEEE 1149.1 boundary-scan capability
1.9.2 Test Clock treatment
1.9.2.1 Test Clock source <\/td>\n<\/tr>\n
65<\/td>\n1.9.2.2 Test Clock shared or dedicated use
1.9.2.3 Unorthodox use of Test Clock <\/td>\n<\/tr>\n
66<\/td>\n1.10 Scalability
1.10.1 Types of operation\/capability classes <\/td>\n<\/tr>\n
68<\/td>\n1.10.2 Signaling
1.11 Flexibility
1.11.1 Supporting various scan topologies <\/td>\n<\/tr>\n
70<\/td>\n1.11.2 Operation with more than one scan topology\/other technologies
1.12 Document content <\/td>\n<\/tr>\n
71<\/td>\n1.12.1 Descriptive material
1.12.2 Specification material
1.13 Document organization
1.13.1 Partitioning <\/td>\n<\/tr>\n
72<\/td>\n1.13.1.1 Foundation <\/td>\n<\/tr>\n
73<\/td>\n1.13.1.2 TAP.7 Classes
1.13.1.3 Test description languages
1.13.1.4 Annexes <\/td>\n<\/tr>\n
74<\/td>\n1.13.2 Pictorial view <\/td>\n<\/tr>\n
75<\/td>\n1.14 Using the standard
1.14.1 User background knowledge
1.14.2 Types of users
1.14.2.1 Chip designer
1.14.2.2 Programmer
1.14.3 Use summary <\/td>\n<\/tr>\n
76<\/td>\n1.15 Conventions <\/td>\n<\/tr>\n
82<\/td>\n2. Normative references <\/td>\n<\/tr>\n
83<\/td>\n3. Definitions, acronyms, and abbreviations
3.1 Definitions <\/td>\n<\/tr>\n
87<\/td>\n3.2 Acronyms and abbreviations <\/td>\n<\/tr>\n
92<\/td>\n4. TAP.7 concepts and architecture
4.1 Introduction
4.2 Concepts supporting system architecture
4.2.1 Maximizing compatibility with IEEE Std 1149.1 <\/td>\n<\/tr>\n
93<\/td>\n4.2.1.1 Hardware components
4.2.1.2 Software components
4.2.2 TAPC hierarchy
4.2.2.1 Overview <\/td>\n<\/tr>\n
94<\/td>\n4.2.2.2 Hierarchy levels <\/td>\n<\/tr>\n
95<\/td>\n4.2.3 Parking the TAPC state
4.2.3.1 Overview <\/td>\n<\/tr>\n
96<\/td>\n4.2.3.2 Parking-state relationships <\/td>\n<\/tr>\n
97<\/td>\n4.2.3.3 Parking-state terminology
4.2.3.3.1 ADTAPC selection states
4.2.3.3.2 CLTAPC selection states <\/td>\n<\/tr>\n
98<\/td>\n4.2.3.3.3 EMTAPC selection states <\/td>\n<\/tr>\n
99<\/td>\n4.2.3.3.4 Selection state summary
4.2.4 Choice of parking states
4.2.5 Parking methods
4.2.6 Operation of the TAP.7 Controller
4.2.6.1 TAP.7 Controller management <\/td>\n<\/tr>\n
100<\/td>\n4.2.6.2 System and Control Paths <\/td>\n<\/tr>\n
101<\/td>\n4.2.6.3 Power management <\/td>\n<\/tr>\n
102<\/td>\n4.2.7 Scan topologies
4.2.7.1 Series and Star Scan Topologies <\/td>\n<\/tr>\n
103<\/td>\n4.2.7.2 Scan Topology Training
4.2.7.3 Sharing of signaling with other technologies
4.2.7.4 Direct addressability for Star Scan Topologies <\/td>\n<\/tr>\n
104<\/td>\n4.2.7.5 Series-Equivalent Scans for Star Scan Topologies <\/td>\n<\/tr>\n
105<\/td>\n4.2.7.6 Output-drive characteristics <\/td>\n<\/tr>\n
106<\/td>\n4.2.7.7 Scan formats <\/td>\n<\/tr>\n
107<\/td>\n4.2.7.8 Interoperability
4.3 Concepts supporting pin efficiency
4.3.1 Signaling methods <\/td>\n<\/tr>\n
108<\/td>\n4.3.2 Protocols
4.3.2.1 Protocol types <\/td>\n<\/tr>\n
109<\/td>\n4.3.2.2 Standard Protocol
4.3.2.3 Advanced Protocol <\/td>\n<\/tr>\n
110<\/td>\n4.3.2.3.1 Interleaving of scan and non-scan information <\/td>\n<\/tr>\n
111<\/td>\n4.3.2.3.2 Serialization of scan information <\/td>\n<\/tr>\n
112<\/td>\n4.3.2.4 Control Protocol
4.3.3 Advanced and Control Protocol characteristics
4.3.3.1 Packets, bit-frames, and bits <\/td>\n<\/tr>\n
113<\/td>\n4.3.3.2 Data and control information <\/td>\n<\/tr>\n
114<\/td>\n4.3.4 Performance
4.3.4.1 TAP operation
4.3.4.1.1 Signal timing <\/td>\n<\/tr>\n
115<\/td>\n4.3.4.1.2 Registering of signals
4.3.4.2 Scan transfer efficiency
4.4 Concepts supporting capability
4.4.1 Concepts already described <\/td>\n<\/tr>\n
116<\/td>\n4.4.2 Resets
4.4.3 Private commands and registers
4.5 IEEE 1149.7 architecture
4.5.1 Components <\/td>\n<\/tr>\n
119<\/td>\n4.5.2 Reset types <\/td>\n<\/tr>\n
120<\/td>\n4.5.3 Start-up options <\/td>\n<\/tr>\n
121<\/td>\n4.6 Operating models
4.6.1 Model types
4.6.2 Standard models <\/td>\n<\/tr>\n
123<\/td>\n4.6.3 Advanced models <\/td>\n<\/tr>\n
124<\/td>\n5. T0\u2013T3 TAP.7 operational overview
5.1 Introduction
5.2 T0 TAP.7
5.2.1 Overview <\/td>\n<\/tr>\n
125<\/td>\n5.2.2 Operating modes and capabilities <\/td>\n<\/tr>\n
126<\/td>\n5.2.3 Operation
5.2.3.1 Multi-TAPC architecture
5.2.3.2 Selection and deselection of EMTAPCs <\/td>\n<\/tr>\n
127<\/td>\n5.2.4 T0 TAP.7 high-level block diagram <\/td>\n<\/tr>\n
128<\/td>\n5.3 T1 TAP.7
5.3.1 Overview <\/td>\n<\/tr>\n
129<\/td>\n5.3.2 Operating modes and capabilities
5.3.3 Operation
5.3.3.1 Adding TAP.7 functionality to the BYPASS and IDCODE instructions
5.3.3.2 Zero-bit DR scans <\/td>\n<\/tr>\n
130<\/td>\n5.3.3.3 Utilizing ZBSs for TAP.7 Controller functionality
5.3.3.3.1 Locking the ZBS count
5.3.3.3.2 Control levels <\/td>\n<\/tr>\n
131<\/td>\n5.3.3.3.3 Exiting a control level
5.3.3.3.4 Zeroing the ZBS count
5.3.3.4 EPU Operating States
5.3.3.5 Commands <\/td>\n<\/tr>\n
134<\/td>\n5.3.3.6 Registers <\/td>\n<\/tr>\n
136<\/td>\n5.3.3.7 Using the System and Control Paths <\/td>\n<\/tr>\n
137<\/td>\n5.3.3.7.1 System Path
5.3.3.7.2 Control Path <\/td>\n<\/tr>\n
138<\/td>\n5.3.3.7.3 TDO Drive Policy
5.3.3.8 EPU groups
5.3.4 T1 TAP.7 high-level block diagram
5.4 T2 TAP.7
5.4.1 Overview <\/td>\n<\/tr>\n
140<\/td>\n5.4.2 Operating modes and capabilities <\/td>\n<\/tr>\n
141<\/td>\n5.4.3 Operation
5.4.3.1 Overview <\/td>\n<\/tr>\n
142<\/td>\n5.4.3.2 Using the System and Control Paths <\/td>\n<\/tr>\n
143<\/td>\n5.4.3.3 TDO Drive Policy
5.4.3.4 STL groups
5.4.3.4.1 STL group types <\/td>\n<\/tr>\n
144<\/td>\n5.4.3.4.2 STL Group Membership changes
5.4.4 T2 TAP.7 high-level block diagram <\/td>\n<\/tr>\n
145<\/td>\n5.5 T3 TAP.7
5.5.1 Overview <\/td>\n<\/tr>\n
146<\/td>\n5.5.2 Operating modes and capabilities <\/td>\n<\/tr>\n
148<\/td>\n5.5.3 Operation
5.5.3.1 Within series and star scan topologies
5.5.3.2 T3 TAP.7 Controller addressability in a Star-4 Scan Topology
5.5.3.3 Pause-IR and Pause-DR STL groups <\/td>\n<\/tr>\n
149<\/td>\n5.5.3.4 Series\/star scan equivalency
5.5.3.4.1 Defining scan equivalency
5.5.3.4.2 Creating a Series-Equivalent Scan within a Star Scan Topology <\/td>\n<\/tr>\n
150<\/td>\n5.5.3.5 Scan Selection Directives
5.5.3.5.1 Enabling the use of SSDs
5.5.3.5.2 Types of SSDs <\/td>\n<\/tr>\n
151<\/td>\n5.5.3.5.3 SSD execution
5.5.3.5.4 SSD State Machine <\/td>\n<\/tr>\n
152<\/td>\n5.5.3.6 Series-Equivalent Scan creation <\/td>\n<\/tr>\n
153<\/td>\n5.5.3.6.1 Exclusivity of SSD and TAP.7 Controller commands <\/td>\n<\/tr>\n
154<\/td>\n5.5.3.7 Using the System and Control Paths <\/td>\n<\/tr>\n
155<\/td>\n5.5.3.8 TDO Drive Policy
5.5.4 T3 TAP.7 high-level block diagram <\/td>\n<\/tr>\n
157<\/td>\n6. T4\u2013T5 TAP.7 operational overview
6.1 Introduction <\/td>\n<\/tr>\n
158<\/td>\n6.2 T4 TAP.7
6.2.1 Operating modes and capabilities <\/td>\n<\/tr>\n
159<\/td>\n6.2.2 Operation
6.2.2.1 Signal behaviors
6.2.2.2 Rising and falling TMSC input sampling <\/td>\n<\/tr>\n
160<\/td>\n6.2.2.3 Controller addressability in a Star-2 Scan Topology
6.2.2.4 RSU and APU functions <\/td>\n<\/tr>\n
162<\/td>\n6.2.2.4.1 Bypass (BPA)
6.2.2.4.2 Check Process Active (CPA) <\/td>\n<\/tr>\n
165<\/td>\n6.2.2.4.3 Scan Packet Active (SPA) <\/td>\n<\/tr>\n
166<\/td>\n6.2.3 T4 TAP.7 high-level block diagram <\/td>\n<\/tr>\n
167<\/td>\n6.3 T5 TAP.7
6.3.1 Overview <\/td>\n<\/tr>\n
169<\/td>\n6.3.2 Operating modes and capabilities
6.3.2.1 Transport source\/destinations
6.3.2.1.1 Single-client operation <\/td>\n<\/tr>\n
170<\/td>\n6.3.2.1.2 Multi-client operation <\/td>\n<\/tr>\n
171<\/td>\n6.3.2.1.3 Client-to-client operation <\/td>\n<\/tr>\n
172<\/td>\n6.3.2.2 Transfer characteristics <\/td>\n<\/tr>\n
173<\/td>\n6.3.3 Operation
6.3.3.1 Transport Control Function <\/td>\n<\/tr>\n
174<\/td>\n6.3.3.2 TPA <\/td>\n<\/tr>\n
175<\/td>\n6.3.4 T5 TAP.7 high-level block diagram <\/td>\n<\/tr>\n
176<\/td>\n6.4 TAP.7 feature summary <\/td>\n<\/tr>\n
178<\/td>\n7. System concepts
7.1 Introduction
7.2 Key system attributes
7.3 DTS\/TS connectivity with a mix of technologies
7.3.1 Technology mixes <\/td>\n<\/tr>\n
179<\/td>\n7.3.2 Technology branches <\/td>\n<\/tr>\n
180<\/td>\n7.4 TAP.7 deployment scenarios
7.4.1 TAP.1 Series Branches
7.4.2 TAP.7 Series, Star-4, and Star-2 Branches <\/td>\n<\/tr>\n
181<\/td>\n7.5 Chip TAPC hierarchy <\/td>\n<\/tr>\n
182<\/td>\n7.6 Combined view of TAP connectivity and TAPC hierarchy <\/td>\n<\/tr>\n
183<\/td>\n7.7 Chips, components, and boards <\/td>\n<\/tr>\n
185<\/td>\n8. TAPC hierarchy
8.1 Introduction
8.2 Selection\/deselection with the TAPC hierarchy
8.2.1 Selection choices <\/td>\n<\/tr>\n
186<\/td>\n8.2.2 Selection\/deselection\/class relationships
8.2.3 TAPC parent\/child relationships
8.3 TAPC selection\/deselection characteristics
8.3.1 TAPC and scan path behavior <\/td>\n<\/tr>\n
187<\/td>\n8.3.2 Selection\/deselection mechanisms
8.3.3 Parking states and resynchronization <\/td>\n<\/tr>\n
188<\/td>\n8.4 ADTAPC selection\/deselection
8.4.1 Parking use cases
8.4.2 DTS\/ADTAPC relationship <\/td>\n<\/tr>\n
189<\/td>\n8.4.3 ADTAPC operation <\/td>\n<\/tr>\n
190<\/td>\n8.5 CLTAPC selection\/deselection
8.5.1 Parking use cases
8.5.2 ADTAPC\/CLTAPC relationship
8.5.3 CLTAPC operation <\/td>\n<\/tr>\n
192<\/td>\n8.6 EMTAPC selection\/deselection
8.6.1 Parking use cases
8.6.2 CLTAPC\/EMTAPC relationship
8.6.3 EMTAPC operation <\/td>\n<\/tr>\n
193<\/td>\n8.7 Using a common selection\/deselection protocol across technologies
8.8 RSU deployment
8.8.1 Use with new or existing IP <\/td>\n<\/tr>\n
194<\/td>\n8.8.2 Using TAP pins for multiple functions
8.9 Using the TAPC hierarchy
8.9.1 Selection considerations <\/td>\n<\/tr>\n
195<\/td>\n8.9.2 Start-up considerations
8.10 Test\/debug applications and the TAPC hierarchy
8.10.1 Debug use of the TAPC hierarchy <\/td>\n<\/tr>\n
196<\/td>\n8.10.2 Test use of the TAPC hierarchy <\/td>\n<\/tr>\n
198<\/td>\n9. Registers, commands, and scan paths
9.1 Introduction
9.2 Command basics <\/td>\n<\/tr>\n
200<\/td>\n9.3 Register portfolio
9.3.1 Description
9.3.1.1 Global and Local Registers
9.3.1.2 Register loads <\/td>\n<\/tr>\n
201<\/td>\n9.3.1.3 Register reset values
9.3.2 Specifications <\/td>\n<\/tr>\n
203<\/td>\n9.4 Command portfolio
9.4.1 Description
9.4.1.1 Command types
9.4.1.2 Store commands <\/td>\n<\/tr>\n
204<\/td>\n9.4.1.3 Select commands
9.4.1.4 Scan commands
9.4.1.5 Enumerate commands
9.4.1.6 Private commands
9.4.1.7 Effects a TAP.7 Controller reset <\/td>\n<\/tr>\n
205<\/td>\n9.4.2 Specifications <\/td>\n<\/tr>\n
210<\/td>\n9.5 Representation of commands in examples
9.6 Global and Local Register programming with commands <\/td>\n<\/tr>\n
211<\/td>\n9.7 1Scan paths
9.7.1 Conceptual and physical views
9.7.1.1 Description
9.7.1.1.1 Path characteristics
9.7.1.1.2 Conceptual path selection <\/td>\n<\/tr>\n
212<\/td>\n9.7.1.1.3 Physical path selection <\/td>\n<\/tr>\n
213<\/td>\n9.7.1.2 Specifications <\/td>\n<\/tr>\n
215<\/td>\n9.7.2 EPU Scan Paths and their selection
9.7.2.1 Description
9.7.2.2 Specifications <\/td>\n<\/tr>\n
216<\/td>\n9.7.3 EPU Scan Path characteristics
9.7.3.1 Description
9.7.3.1.1 Scan-path continuity <\/td>\n<\/tr>\n
217<\/td>\n9.7.3.1.2 EPU Bypass-Path characteristics
9.7.3.1.3 EPU Bit-Path characteristics
9.7.3.1.4 EPU String-Path characteristics <\/td>\n<\/tr>\n
220<\/td>\n9.7.3.1.5 Enumerate-Path characteristics
9.7.3.1.6 Auxiliary Path
9.7.3.2 Specifications <\/td>\n<\/tr>\n
222<\/td>\n9.8 Two-part commands
9.9 Three-part commands
9.9.1 SCNB Command characteristics <\/td>\n<\/tr>\n
223<\/td>\n9.9.2 SCNS Command characteristics <\/td>\n<\/tr>\n
224<\/td>\n9.9.3 CIDA Command characteristics <\/td>\n<\/tr>\n
226<\/td>\n9.10 RDBACKx and CNFGx Registers <\/td>\n<\/tr>\n
227<\/td>\n9.10.1 RDBACKx Registers
9.10.1.1 Description
9.10.1.2 Specifications <\/td>\n<\/tr>\n
228<\/td>\n9.10.2 CNFGx Registers
9.10.2.1 Description
9.10.2.1.1 Overview <\/td>\n<\/tr>\n
229<\/td>\n9.10.2.1.2 CNFG0 mandatory configuration information
9.10.2.1.3 CNFG0 optional configuration information <\/td>\n<\/tr>\n
230<\/td>\n9.10.2.1.4 CNFG1 optional configuration information
9.10.2.1.5 CNFG2 and CNFG3 Registers
9.10.2.1.6 Determining the TAP type and class using configuration information
9.10.2.2 Specifications <\/td>\n<\/tr>\n
232<\/td>\n9.11 An approach to implementing command processing and scan paths <\/td>\n<\/tr>\n
236<\/td>\n10. RSU ancillary services
10.1 Introduction
10.2 Resets
10.2.1 Description
10.2.1.1 Overview <\/td>\n<\/tr>\n
237<\/td>\n10.2.1.2 Reset considerations
10.2.1.3 Reset effects <\/td>\n<\/tr>\n
238<\/td>\n10.2.1.3.1 Type-5 Reset
10.2.1.3.2 Type-4 Reset
10.2.1.3.3 Type-3 Reset <\/td>\n<\/tr>\n
239<\/td>\n10.2.1.3.4 Type-2 Reset
10.2.1.3.5 Type-1 Reset
10.2.1.3.6 Type-0 Reset
10.2.1.3.7 Type-0 versus a Type-2 Reset
10.2.1.4 144BTAP.7 Controller operation is ensured after power-up
10.2.1.5 Other effects of a TAP.7 Controller reset <\/td>\n<\/tr>\n
240<\/td>\n10.2.1.6 An approach to implementing TAP.7 Controller resets <\/td>\n<\/tr>\n
241<\/td>\n10.2.2 Specifications <\/td>\n<\/tr>\n
243<\/td>\n10.3 Start-up options
10.3.1 Description
10.3.1.1 Overview <\/td>\n<\/tr>\n
244<\/td>\n10.3.1.2 1149.1-compliant behavior start-up option
10.3.1.3 1149.1-Compatible Start-up option <\/td>\n<\/tr>\n
245<\/td>\n10.3.1.4 IEEE 1149.1-Protocol Compatible
10.3.1.5 Offline-at-Start-up option <\/td>\n<\/tr>\n
246<\/td>\n10.3.1.6 Start-up behavior <\/td>\n<\/tr>\n
247<\/td>\n10.3.2 Specifications <\/td>\n<\/tr>\n
251<\/td>\n10.4 Escape Detection
10.4.1 Description
10.4.1.1 Overview <\/td>\n<\/tr>\n
252<\/td>\n10.4.1.2 Detection <\/td>\n<\/tr>\n
253<\/td>\n10.4.1.2.1 Custom Escape
10.4.1.2.2 Selection and Deselection Escapes <\/td>\n<\/tr>\n
254<\/td>\n10.4.1.3 Reset Escape
10.4.1.4 Timing considerations
10.4.1.5 An approach to implementing Escape Detection <\/td>\n<\/tr>\n
256<\/td>\n10.4.2 Specifications <\/td>\n<\/tr>\n
257<\/td>\n10.5 Selection Alert
10.5.1 Description
10.5.1.1 Overview <\/td>\n<\/tr>\n
258<\/td>\n10.5.1.2 Selection Alert Bit Sequence <\/td>\n<\/tr>\n
259<\/td>\n10.5.1.3 Selection Alert detection
10.5.1.4 An approach to implementing Selection Alerts <\/td>\n<\/tr>\n
261<\/td>\n10.5.2 Specifications <\/td>\n<\/tr>\n
263<\/td>\n10.6 Deselection Alert
10.6.1 Description
10.6.2 Specifications <\/td>\n<\/tr>\n
264<\/td>\n10.7 Programming considerations
10.7.1 Resets
10.7.2 Escapes
10.7.3 Selection Alerts
10.7.4 Test and debug
10.7.5 Concurrent use of a Selection Escape and Selection Alert <\/td>\n<\/tr>\n
265<\/td>\n10.8 ADTAPC State Machine
10.8.1 Need
10.8.2 An approach to implementing the ADTAPC <\/td>\n<\/tr>\n
267<\/td>\n11. RSU Online\/Offline capability
11.1 Introduction
11.2 Managing Online\/Offline operation <\/td>\n<\/tr>\n
268<\/td>\n11.3 Online\/Offline operating principles
11.3.1 Conceptual view of Online\/Offline operation <\/td>\n<\/tr>\n
269<\/td>\n11.3.2 Events affecting Online\/Offline operation <\/td>\n<\/tr>\n
270<\/td>\n11.3.3 Summary of responses to selection\/deselection events
11.3.4 Interoperability with other technologies <\/td>\n<\/tr>\n
272<\/td>\n11.4 Initiating Offline operation
11.4.1 Description
11.4.1.1 Events initiating Offline operation
11.4.1.2 Escapes <\/td>\n<\/tr>\n
273<\/td>\n11.4.1.3 Alerts
11.4.1.4 Use of an unsupported feature
11.4.1.5 Offline-at-Start-up
11.4.2 Specifications
11.5 Initiating Online operation
11.5.1 Description <\/td>\n<\/tr>\n
274<\/td>\n11.5.2 Specifications
11.6 Context-sensitive response to Selection and Deselection Escapes
11.6.1 Description <\/td>\n<\/tr>\n
275<\/td>\n11.6.1.1 Escape qualification criteria during Online operation
11.6.1.2 Escape qualification criteria during Offline-at-Start-up operation <\/td>\n<\/tr>\n
276<\/td>\n11.6.1.3 Selection Alert during Offline-at-Start-up operation
11.6.2 Specifications <\/td>\n<\/tr>\n
277<\/td>\n11.7 Selection Sequence
11.7.1 Initiation
11.7.2 Format
11.7.3 Technology-independent portion <\/td>\n<\/tr>\n
278<\/td>\n11.7.4 Technology-dependent portion
11.7.5 Forms of Selection Sequence <\/td>\n<\/tr>\n
279<\/td>\n11.7.6 Online Activation Code
11.7.6.1 Description <\/td>\n<\/tr>\n
280<\/td>\n11.7.6.2 Specifications <\/td>\n<\/tr>\n
281<\/td>\nFigure 11-9 \u2014 Selection Escape\/subsequent data timing relationship <\/td>\n<\/tr>\n
282<\/td>\nFigure 11-10 \u2014 Selection Alert\/subsequent data timing relationship
11.7.7 TAP.7 Extension Code
11.7.7.1 Description <\/td>\n<\/tr>\n
283<\/td>\n11.7.7.2 Specifications <\/td>\n<\/tr>\n
284<\/td>\n11.7.8 Global Register load
11.7.8.1 Description <\/td>\n<\/tr>\n
285<\/td>\n11.7.8.2 Specifications
11.7.9 Check Packet
11.7.9.1 Description
11.7.9.1.1 Format <\/td>\n<\/tr>\n
286<\/td>\n11.7.9.1.2 Function <\/td>\n<\/tr>\n
287<\/td>\n11.7.9.1.3 Directives
11.7.9.2 Specifications <\/td>\n<\/tr>\n
288<\/td>\n11.8 Parking-state considerations
11.8.1 Description
11.8.2 Specifications <\/td>\n<\/tr>\n
291<\/td>\n11.9 Control State Machine
11.9.1 Mandatory and optional behaviors
11.9.1.1 Description <\/td>\n<\/tr>\n
292<\/td>\n11.9.1.2 Specifications <\/td>\n<\/tr>\n
293<\/td>\n11.9.2 Standard state (STD)
11.9.2.1 Description
11.9.2.2 Specifications <\/td>\n<\/tr>\n
294<\/td>\n11.9.3 Advanced state (ADV)
11.9.3.1 Description
11.9.3.2 Specifications <\/td>\n<\/tr>\n
295<\/td>\n11.9.4 Offline waiting state (OLW)
11.9.4.1 Description
11.9.4.2 Specifications <\/td>\n<\/tr>\n
296<\/td>\n11.9.5 Test state (TEST)
11.9.5.1 Description
11.9.5.1.1 Selection test <\/td>\n<\/tr>\n
297<\/td>\n11.9.5.1.2 Factors requiring a Global Register load for placement Online
11.9.5.1.3 ADTAPC resynchronization <\/td>\n<\/tr>\n
298<\/td>\n11.9.5.1.4 Priority of conditions causing state changes
11.9.5.1.5 Test state function <\/td>\n<\/tr>\n
299<\/td>\n11.9.5.1.6 Selection Sequences requiring a state load <\/td>\n<\/tr>\n
300<\/td>\n11.9.5.2 Specifications <\/td>\n<\/tr>\n
303<\/td>\n11.9.6 Check Packet state (CHK)
11.9.6.1 Description
11.9.6.1.1 CHK substates <\/td>\n<\/tr>\n
304<\/td>\n11.9.6.1.2 CP examples <\/td>\n<\/tr>\n
306<\/td>\n11.9.6.2 Specifications <\/td>\n<\/tr>\n
309<\/td>\n11.9.7 Offline-at-Start-up state (OLS)
11.9.7.1 Description
11.9.7.1.1 Placement Online
11.9.7.1.2 CLTAPC state initialization <\/td>\n<\/tr>\n
310<\/td>\n11.9.7.1.3 Selection Escape qualification in the OLS state
11.9.7.1.4 Example of exiting the OLS state <\/td>\n<\/tr>\n
311<\/td>\n11.9.7.2 Specifications <\/td>\n<\/tr>\n
312<\/td>\n11.9.7.3 An approach to implementing the CSM <\/td>\n<\/tr>\n
314<\/td>\n11.10 Programming considerations
11.10.1 Escapes
11.10.1.1 Selection Escape
11.10.1.2 Deselection Escape <\/td>\n<\/tr>\n
315<\/td>\n11.10.1.3 Reset Escape
11.10.2 Alerts
11.10.2.1 Deselection Alert
11.10.2.2 Selection Alert
11.10.2.3 Offline-at-Start-up <\/td>\n<\/tr>\n
316<\/td>\n11.10.3 Selection Sequences
11.10.3.1 DTS\/TAP.7 Controller synchronization
11.10.3.2 Short Form
11.10.3.3 Long Form <\/td>\n<\/tr>\n
317<\/td>\n11.10.4 Hang caused by a programming error <\/td>\n<\/tr>\n
318<\/td>\n12. TAP signals
12.1 Introduction
12.2 TAP.7 Class\/signal relationships
12.2.1 Description <\/td>\n<\/tr>\n
319<\/td>\n12.2.2 Specifications <\/td>\n<\/tr>\n
320<\/td>\n12.3 Signal function and bias
12.3.1 Description <\/td>\n<\/tr>\n
321<\/td>\n12.3.2 Specifications <\/td>\n<\/tr>\n
322<\/td>\n12.4 Test Reset (nTRST and nTRST_PD) signals
12.4.1 Description <\/td>\n<\/tr>\n
323<\/td>\n12.4.2 Specifications
12.5 TAP.7 signal functions with corresponding IEEE 1149.1 names
12.5.1 Description
12.5.2 Specifications
12.6 Test Clock (TCK)
12.6.1 Description
12.6.2 Specifications <\/td>\n<\/tr>\n
324<\/td>\n12.7 Test Mode Select (TMS\/TMSC)
12.7.1 Description
12.7.1.1 Online start-up <\/td>\n<\/tr>\n
325<\/td>\n12.7.1.2 Offline start-up <\/td>\n<\/tr>\n
327<\/td>\n12.7.1.3 Combined view of Online and Offline-at-Start-up TMS(C) signal behaviors <\/td>\n<\/tr>\n
330<\/td>\n12.7.2 Specifications <\/td>\n<\/tr>\n
331<\/td>\n12.8 Test Data Input (TDI\/TDIC)
12.8.1 Description <\/td>\n<\/tr>\n
332<\/td>\n12.8.2 Specifications <\/td>\n<\/tr>\n
334<\/td>\n12.9 Test Data Output (TDO\/TDOC)
12.9.1 Description <\/td>\n<\/tr>\n
335<\/td>\n12.9.2 Specifications <\/td>\n<\/tr>\n
336<\/td>\n12.10 Offline-at-Start-up behavior
12.10.1 Description <\/td>\n<\/tr>\n
337<\/td>\n12.10.2 Specifications
12.11 TAP connections
12.11.1 Description
12.11.2 Specifications <\/td>\n<\/tr>\n
338<\/td>\n12.12 Applicability of this standard
12.12.1 Description
12.12.2 Specifications <\/td>\n<\/tr>\n
339<\/td>\n12.13 Recommendations for interoperability
12.13.1 Overview
12.13.2 Power-up behavior
12.13.3 IEEE 1149.7-Non-disruptive behavior
12.13.3.1 Description <\/td>\n<\/tr>\n
340<\/td>\n12.13.3.2 Specifications
12.13.4 IEEE 1149.7-Other Behavior
12.13.4.1 Description
12.13.4.2 Specifications <\/td>\n<\/tr>\n
342<\/td>\n13. TDO(C) Signal Drive Policy
13.1 Introduction
13.2 TDO(C) Signal Drive Types
13.2.1 TDO(C) Signal Drive Types <\/td>\n<\/tr>\n
343<\/td>\n13.2.1.1 Single Drive
13.2.1.2 Joint Drive
13.2.1.3 Voting Drive
13.2.1.4 Inhibited Drive
13.2.2 Wire-ANDed TDOC data created with a combination of drives <\/td>\n<\/tr>\n
344<\/td>\n13.3 Factors affecting the TDO(C) Drive Policy <\/td>\n<\/tr>\n
345<\/td>\n13.4 TDO(C) Drive Policy template
13.4.1 General characteristics
13.4.2 TDOC drive enables
13.4.3 TDO(C) Drive Policy components <\/td>\n<\/tr>\n
346<\/td>\n13.4.4 TAP.7 Class\/TDO(C) Drive Policy component applicability
13.4.5 Dormant TDO(C) Drive Policy
13.4.6 Transition TDO(C) Drive Policy
13.4.7 Series TDO(C) Drive Policy components
13.4.7.1 Series System <\/td>\n<\/tr>\n
347<\/td>\n13.4.7.2 Series Command
13.4.7.3 Series Control Level
13.4.8 Star-4 TDO(C) Drive Policies
13.4.8.1 Star-4 System
13.4.8.2 Star-4 Command <\/td>\n<\/tr>\n
348<\/td>\n13.4.8.3 Star-4 control level
13.4.9 Hierarchical and flat views of the TDO(C) Drive Policy <\/td>\n<\/tr>\n
351<\/td>\n13.4.10 Conceptual diagram of the TDO(C) Drive Policy <\/td>\n<\/tr>\n
352<\/td>\n13.5 T0 TAP.7 TDOC Drive Policy
13.5.1 Description
13.5.2 Specifications <\/td>\n<\/tr>\n
353<\/td>\n13.6 T1 and T2 TAP.7 TDOC Drive Policy
13.6.1 Description <\/td>\n<\/tr>\n
354<\/td>\n13.6.2 Specifications <\/td>\n<\/tr>\n
355<\/td>\n13.7 T3 and above TAP.7 TDOC Drive Policy
13.7.1 Description <\/td>\n<\/tr>\n
356<\/td>\n13.7.2 Specifications <\/td>\n<\/tr>\n
358<\/td>\n13.8 STL Group Membership
13.8.1 Tracking the Group Membership of STLs
13.8.2 STL Group Membership changes
13.8.2.1 Group membership changes with the Test-Logic-Reset state
13.8.2.2 Group membership changes with the Run-Test\/Idle state <\/td>\n<\/tr>\n
359<\/td>\n13.8.2.3 Group membership changes with the Pause-IR state
13.8.2.4 Group membership changes with the Pause-DR state
13.8.3 Commands\/SSDs affecting group Scan Group Candidacy and Membership
13.8.3.1 Commands affecting Scan Group Candidacy <\/td>\n<\/tr>\n
360<\/td>\n13.8.3.2 SSDs affecting Scan Group Candidacy and Membership
13.8.3.2.1 SSDs associated with the Run-Test\/Idle state
13.8.3.2.2 SSDs associated with the Pause-IR state
13.8.3.2.3 SSDs associated with the Pause-DR state <\/td>\n<\/tr>\n
361<\/td>\n13.8.4 Only Scan Group Member determination
13.8.4.1 Criteria
13.8.4.2 Method and information used to make determination
13.8.4.2.1 Idle Group Membership and membership counts <\/td>\n<\/tr>\n
362<\/td>\n13.8.4.2.2 Pause-xR Group Membership and membership counts
13.8.4.2.3 Scan Group Membership and membership counts <\/td>\n<\/tr>\n
363<\/td>\n13.8.4.2.4 Information recorded
13.8.5 STL group candidate and membership counts
13.8.5.1 Description
13.8.5.1.1 Scan Group Candidate Count (SGCC) <\/td>\n<\/tr>\n
365<\/td>\n13.8.5.1.2 Potential Scan Group Membership Count Last <\/td>\n<\/tr>\n
366<\/td>\n13.8.5.1.3 Factors creating SGCC and PSGMCL ambiguity
13.8.5.2 Specifications <\/td>\n<\/tr>\n
369<\/td>\n13.8.6 Scan Group Membership Count Last determination
13.8.6.1 Description
13.8.6.2 Specification <\/td>\n<\/tr>\n
370<\/td>\n13.8.7 Only Scan Group Member Last determination
13.8.7.1 Description
13.8.7.2 Specification <\/td>\n<\/tr>\n
372<\/td>\n13.9 EPU Group Membership
13.9.1 Description
13.9.1.1 Tracking the EPU\u2019s Group Membership
13.9.1.2 Conditional Group Member Count <\/td>\n<\/tr>\n
373<\/td>\n13.9.1.3 Only Conditional Group Member determination <\/td>\n<\/tr>\n
374<\/td>\n13.9.2 Specifications <\/td>\n<\/tr>\n
376<\/td>\n13.10 Drive Policy summary <\/td>\n<\/tr>\n
377<\/td>\n13.11 An approach to implementing TDOC Drive Policy
13.11.1 Policy generation <\/td>\n<\/tr>\n
378<\/td>\n13.11.2 Potential Scan Group Member Last
13.11.3 The SGCC and PSGMCL functions <\/td>\n<\/tr>\n
379<\/td>\n13.11.4 Determining Scan Group Only Member Last\/Membership Count Last <\/td>\n<\/tr>\n
380<\/td>\n13.11.5 The CGMC function
13.12 Programming considerations <\/td>\n<\/tr>\n
381<\/td>\n14. TMS(C) Signal Drive Policy
14.1 Introduction
14.2 TMS(C) output bit types
14.2.1 Scan Packet content <\/td>\n<\/tr>\n
382<\/td>\n14.2.2 Transport Packet content <\/td>\n<\/tr>\n
383<\/td>\n14.2.3 Drive relationship with TCKC <\/td>\n<\/tr>\n
384<\/td>\n14.3 Drive policy by output bit type <\/td>\n<\/tr>\n
385<\/td>\n14.4 TMSC Signal Drive Types
14.4.1 TMSC Signal Drive Types <\/td>\n<\/tr>\n
386<\/td>\n14.4.1.1 Single Drive
14.4.1.2 Joint Drive
14.4.1.3 Voting Drive
14.4.1.4 Inhibited Drive
14.4.2 Wire-ANDed TMSC signal values <\/td>\n<\/tr>\n
387<\/td>\n14.5 Dormant Bit Drive Policy
14.5.1 Description
14.5.2 Specifications
14.6 Precharge Bit Drive Policy
14.6.1 Description
14.6.2 Specifications <\/td>\n<\/tr>\n
388<\/td>\n14.7 RDY Bit Drive Policy
14.7.1 Description
14.7.1.1 Characteristics
14.7.1.2 Policy details <\/td>\n<\/tr>\n
389<\/td>\n14.7.1.3 Relationship to CLTAPC selection state changes
14.7.2 Specifications <\/td>\n<\/tr>\n
391<\/td>\n14.8 TDO Bit Drive Policy
14.8.1 Description
14.8.1.1 Characteristics
14.8.1.1.1 Policy details for System Path <\/td>\n<\/tr>\n
392<\/td>\n14.8.1.1.2 Policy details for Control Path
14.8.1.2 Correlation to TDO(C) Drive Policy <\/td>\n<\/tr>\n
393<\/td>\n14.8.1.3 Combined TDO bit drive summary <\/td>\n<\/tr>\n
394<\/td>\n14.8.2 Specifications <\/td>\n<\/tr>\n
395<\/td>\n14.9 Transport Bit Drive Policy
14.9.1 Description <\/td>\n<\/tr>\n
396<\/td>\n14.9.2 Specifications
14.10 An approach to implementing TMSC Drive Policy <\/td>\n<\/tr>\n
400<\/td>\n14.11 Programming considerations <\/td>\n<\/tr>\n
402<\/td>\n15. IEEE 1149.1-compliance concepts
15.1 Introduction
15.2 Background <\/td>\n<\/tr>\n
403<\/td>\n15.3 Test and debug views of a system of interest <\/td>\n<\/tr>\n
404<\/td>\n15.4 An approach to implementing EMTAPC selection\/deselection <\/td>\n<\/tr>\n
405<\/td>\n16. T0 TAP.7
16.1 Introduction
16.2 Deployment <\/td>\n<\/tr>\n
406<\/td>\n16.3 Capabilities
16.4 Configurations
16.4.1 Description
16.4.2 Specifications <\/td>\n<\/tr>\n
407<\/td>\n16.5 Start-up behavior
16.5.1 Description
16.5.2 Specifications
16.6 Supporting multiple on-chip TAPCs <\/td>\n<\/tr>\n
408<\/td>\n16.7 Controlling the selection state of EMTAPCs
16.7.1 Description <\/td>\n<\/tr>\n
409<\/td>\n16.7.2 Specifications <\/td>\n<\/tr>\n
411<\/td>\n16.8 Control via the CLTAPC Instruction Register
16.8.1 Description
16.8.1.1 Exclusion of TAPCs <\/td>\n<\/tr>\n
413<\/td>\n16.8.1.2 Isolation of TAPCs <\/td>\n<\/tr>\n
414<\/td>\n16.8.1.3 CLTAPC output registering of MTCP and MTDP control <\/td>\n<\/tr>\n
415<\/td>\n16.8.2 Specifications
16.9 Control via one or more CLTAPC Data Registers
16.9.1 Description <\/td>\n<\/tr>\n
416<\/td>\n16.9.2 Specifications <\/td>\n<\/tr>\n
417<\/td>\n16.10 Control via internal or external tapc_select signals
16.10.1 Description <\/td>\n<\/tr>\n
418<\/td>\n16.10.2 Specifications <\/td>\n<\/tr>\n
419<\/td>\n16.11 Example use cases <\/td>\n<\/tr>\n
420<\/td>\n16.11.1 IR control method with exclusions of TAPCs
16.11.2 IR control method with isolation of TAPCs <\/td>\n<\/tr>\n
421<\/td>\n16.11.3 DR control method with exclusion of TAPCs
16.11.4 DR control method with isolation of TAPCs <\/td>\n<\/tr>\n
422<\/td>\n16.12 Identification of on-chip TAP controller(s)
16.12.1 Description <\/td>\n<\/tr>\n
423<\/td>\n16.12.2 Specifications
16.13 Multiple dies in one package
16.13.1 Description <\/td>\n<\/tr>\n
424<\/td>\n16.13.1.1 Exposing an IEEE 1149.1 DR for the BYPASS and IDCODE instructions
16.13.1.2 Exposing the complete boundary-scan chain for IEEE 1149.1 instructions
16.13.1.3 BSDL documentation <\/td>\n<\/tr>\n
425<\/td>\n16.13.1.4 Packaging dies <\/td>\n<\/tr>\n
426<\/td>\n16.13.1.5 SiP-TAP POR* functionality
16.13.1.6 DR-wire bypass <\/td>\n<\/tr>\n
427<\/td>\n16.13.2 Specifications <\/td>\n<\/tr>\n
428<\/td>\n16.14 Managing STL Group Membership
16.15 RSU operation
16.15.1 Description
16.15.2 Specifications <\/td>\n<\/tr>\n
429<\/td>\n16.16 Programming considerations <\/td>\n<\/tr>\n
430<\/td>\n17. Extended concepts
17.1 Introduction
17.2 Suitability of BYPASS and IDCODE instructions for extended control
17.3 ZBS detection
17.3.1 Description <\/td>\n<\/tr>\n
431<\/td>\n17.3.2 Specifications
17.4 Incrementing, locking, and clearing the ZBS count
17.4.1 Description <\/td>\n<\/tr>\n
432<\/td>\n17.4.2 Specifications <\/td>\n<\/tr>\n
434<\/td>\n17.5 Shared use of ZBSs by the EPU and STL
17.5.1 Description
17.5.1.1 EPU Operating States <\/td>\n<\/tr>\n
435<\/td>\n17.5.1.2 EPU Operating State characteristics <\/td>\n<\/tr>\n
436<\/td>\n17.5.1.3 ZBS use that is compatible with EPU Operating States <\/td>\n<\/tr>\n
437<\/td>\n17.5.1.4 An approach to implementing EPU Operating States <\/td>\n<\/tr>\n
439<\/td>\n17.5.2 Specifications <\/td>\n<\/tr>\n
440<\/td>\n17.6 EPU functionality associated with the ZBS count
17.6.1 Description
17.6.2 Specifications <\/td>\n<\/tr>\n
441<\/td>\n17.7 Programming considerations <\/td>\n<\/tr>\n
442<\/td>\n18. T1 TAP.7
18.1 Introduction <\/td>\n<\/tr>\n
443<\/td>\n18.2 Deployment
18.3 Capabilities
18.3.1 Inherited <\/td>\n<\/tr>\n
444<\/td>\n18.3.2 New
18.4 Register and command portfolio
18.4.1 Description
18.4.1.1 General information <\/td>\n<\/tr>\n
445<\/td>\n18.4.1.2 Register acronyms <\/td>\n<\/tr>\n
446<\/td>\n18.4.1.3 Global Registers
18.4.1.4 Registers already described
18.4.1.5 New register descriptions
18.4.2 Specifications <\/td>\n<\/tr>\n
448<\/td>\n18.5 Configurations
18.5.1 Description
18.5.2 Specifications <\/td>\n<\/tr>\n
449<\/td>\n18.6 Start-up behavior
18.6.1 Description
18.6.2 Specifications
18.7 Conditional Group Membership <\/td>\n<\/tr>\n
450<\/td>\n18.8 Test Reset
18.8.1 Description <\/td>\n<\/tr>\n
451<\/td>\n18.8.2 Specifications <\/td>\n<\/tr>\n
452<\/td>\n18.9 Functional reset
18.9.1 Description <\/td>\n<\/tr>\n
454<\/td>\n18.9.2 Specifications <\/td>\n<\/tr>\n
456<\/td>\n18.10 Power control
18.10.1 Description
18.10.1.1 Overview <\/td>\n<\/tr>\n
457<\/td>\n18.10.1.1.1 Use cases
18.10.1.1.2 Power-control options <\/td>\n<\/tr>\n
458<\/td>\n18.10.1.1.3 Power management within a typical system <\/td>\n<\/tr>\n
459<\/td>\n18.10.1.1.4 Power-control topics
18.10.1.2 Power-Control Model
18.10.1.2.1 TAP.7 Controller power-management states <\/td>\n<\/tr>\n
460<\/td>\n18.10.1.2.2 Key model attributes <\/td>\n<\/tr>\n
461<\/td>\n18.10.1.3 The chip-level power manager\u2019s role in power control
18.10.1.3.1 Responsibilities
18.10.1.3.2 Interaction with TAP.7 Controller <\/td>\n<\/tr>\n
462<\/td>\n18.10.1.3.3 Periods when a Type-0 Reset is asserted
18.10.1.3.4 Handling of power-up and power-down requests <\/td>\n<\/tr>\n
463<\/td>\n18.10.1.3.5 Chip-Level power-up and power-down enables
18.10.1.3.6 The default Power-Control Mode <\/td>\n<\/tr>\n
464<\/td>\n18.10.1.4 The DTS\u2019 role in power control
18.10.1.4.1 Responsibilities
18.10.1.4.2 Directed power-up <\/td>\n<\/tr>\n
465<\/td>\n18.10.1.4.3 Detected power-up <\/td>\n<\/tr>\n
466<\/td>\n18.10.1.5 The TAP.7 Controller\u2019s role in power control
18.10.1.5.1 Responsibilities
18.10.1.5.2 Operation <\/td>\n<\/tr>\n
467<\/td>\n18.10.1.5.3 Test periods <\/td>\n<\/tr>\n
468<\/td>\n18.10.1.5.4 Power-up confirmation test
18.10.1.5.5 Power-down initiation test <\/td>\n<\/tr>\n
469<\/td>\n18.10.1.5.6 Power-down request summary
18.10.1.5.7 Awaiting power-down with the TAP.7 Controller operation shutdown <\/td>\n<\/tr>\n
470<\/td>\n18.10.1.6 Example power-down sequences <\/td>\n<\/tr>\n
472<\/td>\n18.10.1.7 An approach to implementing power control
18.10.2 Specifications <\/td>\n<\/tr>\n
477<\/td>\n18.11 RSU operation
18.11.1 Description <\/td>\n<\/tr>\n
478<\/td>\n18.11.2 Specifications
18.12 Programming considerations <\/td>\n<\/tr>\n
479<\/td>\n19. T2 TAP.7
19.1 Introduction <\/td>\n<\/tr>\n
481<\/td>\n19.2 Deployment
19.3 Capabilities
19.3.1 Inherited
19.3.2 New <\/td>\n<\/tr>\n
482<\/td>\n19.4 Register and command portfolio
19.4.1 Description
19.4.1.1 General information
19.4.1.2 Register acronyms
19.4.1.3 Effects of a Long-Form Selection Sequence
19.4.1.4 New register descriptions <\/td>\n<\/tr>\n
483<\/td>\n19.4.2 Specifications <\/td>\n<\/tr>\n
484<\/td>\n19.5 Configurations
19.5.1 Description
19.5.2 Specifications
19.6 Start-up behavior
19.6.1 Description
19.6.2 Specifications <\/td>\n<\/tr>\n
485<\/td>\n19.7 Scan formats
19.7.1 Description
19.7.2 Specifications
19.8 STL Group Membership
19.8.1 Description
19.8.1.1 Factors affecting group membership <\/td>\n<\/tr>\n
486<\/td>\n19.8.1.2 Reset effects
19.8.1.3 TAPC state effects
19.8.1.4 Control Path effects <\/td>\n<\/tr>\n
488<\/td>\n19.8.1.5 Parked state\/selection relationships <\/td>\n<\/tr>\n
489<\/td>\n19.8.1.6 Concurrent CLTAPC and EMTAPC selection changes <\/td>\n<\/tr>\n
490<\/td>\n19.8.1.7 An approach to implementing CLTAPC selection with the T2 Class <\/td>\n<\/tr>\n
492<\/td>\n19.8.2 Specifications <\/td>\n<\/tr>\n
494<\/td>\n19.9 RSU operation
19.9.1 Description
19.9.2 Specifications <\/td>\n<\/tr>\n
495<\/td>\n19.10 Programming considerations <\/td>\n<\/tr>\n
496<\/td>\n20. T3 TAP.7
20.1 Introduction <\/td>\n<\/tr>\n
498<\/td>\n20.2 Deployment <\/td>\n<\/tr>\n
499<\/td>\n20.3 Capabilities
20.3.1 Inherited
20.3.2 New
20.4 Register and command portfolio
20.4.1 Description
20.4.1.1 General information <\/td>\n<\/tr>\n
500<\/td>\n20.4.1.2 Register acronyms
20.4.1.3 Effect of a Long-Form Selection Sequence
20.4.2 Specifications <\/td>\n<\/tr>\n
501<\/td>\n20.5 Configurations
20.5.1 Description <\/td>\n<\/tr>\n
502<\/td>\n20.5.2 Specifications
20.6 Start-up behavior
20.6.1 Description
20.6.2 Specifications
20.7 Scan formats
20.7.1 Description <\/td>\n<\/tr>\n
503<\/td>\n20.7.2 Specifications
20.8 TAP.7 Controller Address (TCA)
20.8.1 Description <\/td>\n<\/tr>\n
504<\/td>\n20.8.2 Specifications <\/td>\n<\/tr>\n
505<\/td>\n20.9 Aliasing the TCA to a Controller ID
20.9.1 Description
20.9.1.1 CID Allocate Command (CIDA) <\/td>\n<\/tr>\n
506<\/td>\n20.9.1.1.1 CID-allocation criteria
20.9.1.1.2 CID-allocation candidates
20.9.1.1.3 CID-allocation process <\/td>\n<\/tr>\n
507<\/td>\n20.9.1.1.4 Directed CID Allocation
20.9.1.1.5 Undirected CID Allocation
20.9.1.2 External AT generation with the JScan3 Scan Format <\/td>\n<\/tr>\n
508<\/td>\n20.9.1.3 CID-allocation examples <\/td>\n<\/tr>\n
509<\/td>\n20.9.1.4 An approach to implementing CID allocation <\/td>\n<\/tr>\n
510<\/td>\n20.9.2 Specifications <\/td>\n<\/tr>\n
513<\/td>\n20.10 Scan Selection Directives
20.10.1 Description
20.10.1.1 Overview <\/td>\n<\/tr>\n
514<\/td>\n20.10.1.2 SSD format
20.10.1.3 SSD effects on STL Group Membership <\/td>\n<\/tr>\n
515<\/td>\n20.10.1.4 Enabling SSD processing
20.10.1.5 SSD processing <\/td>\n<\/tr>\n
518<\/td>\n20.10.1.6 Conditional SSD execution
20.10.1.7 SSD interaction with other controller functions
20.10.1.8 SSD State Machine <\/td>\n<\/tr>\n
520<\/td>\n20.10.1.9 SSD states allowing Scan Group Membership <\/td>\n<\/tr>\n
521<\/td>\n20.10.1.9.1 Using SSDs to create Series and Star-Equivalent Scans
20.10.1.9.2 Examples of SSD use <\/td>\n<\/tr>\n
526<\/td>\n20.10.1.10 An approach to implementing the SSD function <\/td>\n<\/tr>\n
528<\/td>\n20.10.2 Specifications <\/td>\n<\/tr>\n
532<\/td>\n20.11 Scan Topology Training Sequence
20.11.1 Description
20.11.1.1 Overview
20.11.1.2 Topology Register Function <\/td>\n<\/tr>\n
533<\/td>\n20.11.1.3 Use cases
20.11.1.3.1 Operation with a single TAP.7 Branch <\/td>\n<\/tr>\n
534<\/td>\n20.11.1.3.2 Operation with more than one TAP.7 Branch
20.11.1.4 Scan-path characteristics used to determine the scan topology <\/td>\n<\/tr>\n
535<\/td>\n20.11.1.5 Scan Topology Training Command Sequence <\/td>\n<\/tr>\n
536<\/td>\n20.11.1.5.1 Connectivity test
20.11.1.5.2 Continuity test <\/td>\n<\/tr>\n
537<\/td>\n20.11.2 Specifications
20.12 Managing STL Group Membership
20.12.1 Description
20.12.1.1 Factors affecting group membership
20.12.1.2 An approach to implementing CLTAPC selection with T3 and above classes <\/td>\n<\/tr>\n
539<\/td>\n20.12.2 Specifications <\/td>\n<\/tr>\n
541<\/td>\n20.13 RSU operation
20.13.1 Description <\/td>\n<\/tr>\n
542<\/td>\n20.13.2 Specifications
20.14 Programming considerations <\/td>\n<\/tr>\n
543<\/td>\n21. Advanced concepts
21.1 Architecture <\/td>\n<\/tr>\n
544<\/td>\n21.2 Advanced capabilities
21.2.1 Mandatory and optional capabilities <\/td>\n<\/tr>\n
545<\/td>\n21.2.2 Online and Offline operation
21.2.3 Interoperability with T0\u2013T3 TAP.7s
21.2.4 Interoperability with T4 and above TAP.7s <\/td>\n<\/tr>\n
546<\/td>\n21.3 Comparing the Standard and Advanced Protocols
21.4 APU functions
21.4.1 Conceptual view <\/td>\n<\/tr>\n
547<\/td>\n21.4.2 Bypass Function <\/td>\n<\/tr>\n
548<\/td>\n21.4.3 Scan Function <\/td>\n<\/tr>\n
549<\/td>\n21.4.4 Transport Function <\/td>\n<\/tr>\n
551<\/td>\n21.4.5 Bypass\/Scan\/Control Function interactions
21.5 APU interfaces
21.5.1 TAP <\/td>\n<\/tr>\n
552<\/td>\n21.5.2 EPU
21.5.3 DCC <\/td>\n<\/tr>\n
554<\/td>\n21.6 APU function\/Operating State relationships
21.6.1 Operating State\/function relationships <\/td>\n<\/tr>\n
555<\/td>\n21.6.2 APU Operating State changes <\/td>\n<\/tr>\n
556<\/td>\n21.6.3 Example operating state sequences <\/td>\n<\/tr>\n
558<\/td>\n21.7 TAPC state\/packet relationships
21.7.1 TAPC state and packet sequence relationships <\/td>\n<\/tr>\n
560<\/td>\n21.7.2 Constructing packet sequences <\/td>\n<\/tr>\n
561<\/td>\n21.7.3 Packet combinations\/TAPC state relationships
21.7.4 Scheduling of packets <\/td>\n<\/tr>\n
563<\/td>\n21.8 User\u2019s and implementer\u2019s views of the Advanced Protocol
21.8.1 User\u2019s view <\/td>\n<\/tr>\n
564<\/td>\n21.8.2 Implementer\u2019s view
21.9 An approach to implementing APU Operating State scheduling <\/td>\n<\/tr>\n
566<\/td>\n21.10 Structure of the clauses describing T4 and above TAP.7s <\/td>\n<\/tr>\n
568<\/td>\n22. APU Scan Packets
22.1 CPs
22.2 SPs
22.2.1 Conceptual view of an SP <\/td>\n<\/tr>\n
569<\/td>\n22.2.2 SP format <\/td>\n<\/tr>\n
570<\/td>\n22.2.3 SP content
22.2.3.1 Header Element content
22.2.3.2 Payload Element content <\/td>\n<\/tr>\n
571<\/td>\n22.2.3.3 Delay Element content <\/td>\n<\/tr>\n
572<\/td>\n22.2.4 Types of output bit-frame transactions <\/td>\n<\/tr>\n
573<\/td>\n22.3 SPs that advance the TAPC state <\/td>\n<\/tr>\n
574<\/td>\n22.4 TPs
22.4.1 Conceptual view of a TP
22.4.2 TP format <\/td>\n<\/tr>\n
576<\/td>\n22.4.3 Content
22.5 APU state diagram <\/td>\n<\/tr>\n
578<\/td>\n22.6 An approach to implementing packet scheduling
22.6.1 Pipelining and its effects
22.6.2 SP Element scheduling <\/td>\n<\/tr>\n
579<\/td>\n22.6.3 TP Element scheduling <\/td>\n<\/tr>\n
580<\/td>\n23. T4 TAP.7
23.1 Introduction
23.2 Deployment <\/td>\n<\/tr>\n
581<\/td>\n23.3 Capabilities
23.3.1 Inherited
23.3.2 New <\/td>\n<\/tr>\n
582<\/td>\n23.4 Register and command portfolio
23.4.1 Description
23.4.1.1 General information
23.4.1.2 Register acronyms
23.4.1.3 Effect of a Long-Form Selection Sequence <\/td>\n<\/tr>\n
583<\/td>\n23.4.1.4 New register descriptions
23.4.1.4.1 Auxiliary Pin Function Control (APFC) Register
23.4.1.4.2 Delay Control (DLYC) Register
23.4.1.4.3 Ready Control (RDYC) Register
23.4.1.4.4 Sample Using Rising Edge (SREDGE) Register
23.4.1.4.5 Scan Format (SCNFMT) Register
23.4.1.4.6 System Test Clock Duty Cycle (STCKDC) Register <\/td>\n<\/tr>\n
584<\/td>\n23.4.2 Specifications <\/td>\n<\/tr>\n
586<\/td>\n23.5 Configurations
23.5.1 Description
23.5.2 Specifications <\/td>\n<\/tr>\n
587<\/td>\n23.6 Start-up behavior
23.6.1 Description
23.6.2 Specifications <\/td>\n<\/tr>\n
588<\/td>\n23.7 Scan formats
23.7.1 Description
23.7.1.1 Overview <\/td>\n<\/tr>\n
590<\/td>\n23.7.1.2 Addition of optional scan formats
23.7.1.3 Influences on scan format definition
23.7.1.4 Performance and flexibility tradeoffs <\/td>\n<\/tr>\n
591<\/td>\n23.7.1.5 Comparing the scan formats
23.7.1.5.1 MScan
23.7.1.5.2 OScan <\/td>\n<\/tr>\n
592<\/td>\n23.7.1.5.3 SScan <\/td>\n<\/tr>\n
593<\/td>\n23.7.2 Specification
23.8 Configuration Faults
23.8.1 Description
23.8.2 Specifications <\/td>\n<\/tr>\n
594<\/td>\n23.9 Increasing STL performance
23.9.1 Description <\/td>\n<\/tr>\n
595<\/td>\n23.9.2 Specifications <\/td>\n<\/tr>\n
596<\/td>\n23.10 Auxiliary Pin Function Control
23.10.1 Description <\/td>\n<\/tr>\n
597<\/td>\n23.10.2 Specifications
23.11 Sample Using Rising Edge
23.11.1 Description <\/td>\n<\/tr>\n
598<\/td>\n23.11.2 Specifications
23.12 System and EPU TMS signal values
23.12.1 Description <\/td>\n<\/tr>\n
599<\/td>\n23.12.2 Specifications <\/td>\n<\/tr>\n
600<\/td>\n23.13 System and EPU TDI signal values
23.13.1 Description <\/td>\n<\/tr>\n
601<\/td>\n23.13.2 Specifications <\/td>\n<\/tr>\n
602<\/td>\n23.14 RDY bit values
23.14.1 Description <\/td>\n<\/tr>\n
603<\/td>\n23.14.2 Specifications <\/td>\n<\/tr>\n
604<\/td>\n23.15 TDO bit values
23.15.1 Description <\/td>\n<\/tr>\n
605<\/td>\n23.15.2 Specifications
23.16 Advanced Protocol effects on the EPU\/CLTAPC relationship
23.16.1 Description
23.16.2 Specifications
23.17 SSD detection
23.17.1 Description
23.17.2 Specifications <\/td>\n<\/tr>\n
606<\/td>\n23.18 Programming considerations
23.19 An approach to implementing a TAP.7 Controller with maximum performance <\/td>\n<\/tr>\n
608<\/td>\n24. MScan Scan Format
24.1 Capabilities
24.1.1 Primary purpose
24.1.2 Application types supported <\/td>\n<\/tr>\n
609<\/td>\n24.1.3 Important characteristics
24.2 High-level operation <\/td>\n<\/tr>\n
610<\/td>\n24.3 Scan Packet content
24.3.1 Description
24.3.2 Specifications
24.4 Payload Element
24.4.1 Description
24.4.1.1 Format <\/td>\n<\/tr>\n
611<\/td>\n24.4.1.2 Relationship to EPU signals <\/td>\n<\/tr>\n
612<\/td>\n24.4.1.3 RDY bits <\/td>\n<\/tr>\n
614<\/td>\n24.4.2 Specification
24.5 Delay Element
24.5.1 Description
24.5.1.1 Format <\/td>\n<\/tr>\n
615<\/td>\n24.5.1.2 Delay Element Directives
24.5.1.3 Uses <\/td>\n<\/tr>\n
616<\/td>\n24.5.2 Specifications <\/td>\n<\/tr>\n
617<\/td>\n24.6 Advancing the TAPC state
24.6.1 Description <\/td>\n<\/tr>\n
618<\/td>\n24.6.2 Specifications
24.7 CID allocation
24.7.1 Description <\/td>\n<\/tr>\n
620<\/td>\n24.7.2 Specifications
24.8 Increasing STL performance with the MScan Scan Format
24.9 An approach to implementing the MScan Scan Format
24.9.1 Payload State Machine <\/td>\n<\/tr>\n
622<\/td>\n24.9.2 Ready State Machine <\/td>\n<\/tr>\n
623<\/td>\n24.9.3 Delay State Machine <\/td>\n<\/tr>\n
624<\/td>\n24.10 Where to find examples <\/td>\n<\/tr>\n
625<\/td>\n25. OScan Scan Formats
25.1 Capabilities
25.1.1 Primary purpose
25.1.2 Application types supported <\/td>\n<\/tr>\n
626<\/td>\n25.1.3 Important characteristics
25.2 High-level operation <\/td>\n<\/tr>\n
627<\/td>\n25.3 Scan Packet content
25.3.1 Description
25.3.2 Specifications <\/td>\n<\/tr>\n
628<\/td>\n25.4 Payload Element
25.4.1 Description
25.4.1.1 Format <\/td>\n<\/tr>\n
629<\/td>\n25.4.1.2 Optimizations <\/td>\n<\/tr>\n
630<\/td>\n25.4.1.3 Relationship to EPU signals <\/td>\n<\/tr>\n
634<\/td>\n25.4.1.4 Input bit-frame
25.4.1.5 Drive types <\/td>\n<\/tr>\n
635<\/td>\n25.4.1.6 RDY bits <\/td>\n<\/tr>\n
636<\/td>\n25.4.2 Specifications <\/td>\n<\/tr>\n
637<\/td>\n25.5 Delay Element <\/td>\n<\/tr>\n
638<\/td>\n25.6 Advancing the TAPC state
25.6.1 Description <\/td>\n<\/tr>\n
640<\/td>\n25.6.2 Specifications <\/td>\n<\/tr>\n
641<\/td>\n25.7 CID allocation
25.7.1 Description
25.7.2 Specifications
25.8 Increasing STL performance with OScan Scan Formats <\/td>\n<\/tr>\n
642<\/td>\n25.9 An approach to implementing OScan Scan Formats
25.9.1 Payload State Machine <\/td>\n<\/tr>\n
644<\/td>\n25.9.2 Shift Progress flag <\/td>\n<\/tr>\n
645<\/td>\n25.9.3 CSM and SSM activation
25.9.4 RDY State Machine <\/td>\n<\/tr>\n
646<\/td>\n25.9.5 TAP advance
25.10 Where to find examples <\/td>\n<\/tr>\n
647<\/td>\n26. SScan Scan Formats
26.1 Capabilities
26.1.1 Primary purpose <\/td>\n<\/tr>\n
648<\/td>\n26.1.2 Application types supported <\/td>\n<\/tr>\n
649<\/td>\n26.1.3 Control Segments <\/td>\n<\/tr>\n
650<\/td>\n26.1.4 Data Segments
26.1.5 Stall profiles <\/td>\n<\/tr>\n
651<\/td>\n26.1.6 Important characteristics
26.2 High-level operation
26.2.1 Overview <\/td>\n<\/tr>\n
652<\/td>\n26.2.2 Segments and their use
26.2.2.1 Description
26.2.2.1.1 Use with a TAP.1-like component <\/td>\n<\/tr>\n
653<\/td>\n26.2.2.1.2 Use with a DMA or FIFO component <\/td>\n<\/tr>\n
654<\/td>\n26.2.2.1.3 Use with a direct-access data-rate-dependent component
26.2.2.1.4 Use with a buffered TDI\/TMS component <\/td>\n<\/tr>\n
655<\/td>\n26.2.2.1.5 Utilizing the same scan format for two applications types <\/td>\n<\/tr>\n
656<\/td>\n26.2.2.2 Specifications
26.3 Scan Packet content
26.3.1 Description <\/td>\n<\/tr>\n
657<\/td>\n26.3.2 Specifications <\/td>\n<\/tr>\n
658<\/td>\n26.4 Header Element
26.4.1 Description
26.4.2 Specifications <\/td>\n<\/tr>\n
659<\/td>\n26.5 Payload Element
26.5.1 Description
26.5.1.1 Factors determining payload content <\/td>\n<\/tr>\n
661<\/td>\n26.5.1.2 Optimizations <\/td>\n<\/tr>\n
664<\/td>\n26.5.1.3 Input bit-frame <\/td>\n<\/tr>\n
667<\/td>\n26.5.1.4 Output bit-frame
26.5.1.4.1 Content
26.5.1.4.2 SScan0\/1 output-only segments <\/td>\n<\/tr>\n
668<\/td>\n26.5.1.4.3 SScan2\/3 output-only segments <\/td>\n<\/tr>\n
672<\/td>\n26.5.2 Specifications <\/td>\n<\/tr>\n
674<\/td>\n26.6 Delay Element <\/td>\n<\/tr>\n
675<\/td>\n26.7 Packet sequences and factors influencing them
26.7.1 Description <\/td>\n<\/tr>\n
677<\/td>\n26.7.2 Specifications <\/td>\n<\/tr>\n
678<\/td>\n26.8 Advancing the TAPC state
26.8.1 Description
26.8.1.1 SP followed by a CP
26.8.1.2 Control Segments
26.8.1.3 Data Segments <\/td>\n<\/tr>\n
682<\/td>\n26.8.2 Specifications
26.9 CID allocation
26.9.1 Description
26.9.2 Specifications <\/td>\n<\/tr>\n
683<\/td>\n26.10 Increasing STL performance with SScan Scan Formats
26.11 An approach to implementing SScan Scan Formats
26.11.1 Payload State Machine <\/td>\n<\/tr>\n
684<\/td>\n26.11.2 Escape Detection State Machine <\/td>\n<\/tr>\n
685<\/td>\n26.11.3 Shift Progress flag <\/td>\n<\/tr>\n
686<\/td>\n26.11.4 TAP advance
26.11.5 Additional entry point loads for output-only segments <\/td>\n<\/tr>\n
687<\/td>\n26.11.6 Header Register <\/td>\n<\/tr>\n
688<\/td>\n26.11.7 Timing diagrams <\/td>\n<\/tr>\n
690<\/td>\n26.12 Where to find examples <\/td>\n<\/tr>\n
691<\/td>\n27. T5 TAP.7
27.1 Introduction <\/td>\n<\/tr>\n
692<\/td>\n27.2 Deployment <\/td>\n<\/tr>\n
693<\/td>\n27.3 Capabilities
27.3.1 Inherited
27.3.2 New
27.4 Register and command portfolio
27.4.1 Description
27.4.1.1 General information <\/td>\n<\/tr>\n
694<\/td>\n27.4.1.2 Register acronyms
27.4.1.3 Effect of a Long-Form Selection Sequence
27.4.1.4 Transport protocol revision (TPPREV) register <\/td>\n<\/tr>\n
695<\/td>\n27.4.1.5 Transport states (TPST)
27.4.1.6 Data Element length (TP_DELN)
27.4.1.7 Physical Data Channel to Logical Data Channel association (PDCx_LCA)
27.4.1.8 Physical Data Channel selected (PDCx_SEL)
27.4.1.9 Physical Data Channel DCC selection (PDCx_DCC)
27.4.1.10 Physical Data Channel DCC Control Registers (PDCx_DCCy_CRz) <\/td>\n<\/tr>\n
696<\/td>\n27.4.2 Specifications <\/td>\n<\/tr>\n
700<\/td>\n27.5 Configurations
27.5.1 Description <\/td>\n<\/tr>\n
701<\/td>\n27.5.2 Specifications <\/td>\n<\/tr>\n
702<\/td>\n27.6 Start-up behavior
27.6.1 Description
27.6.2 Specifications
27.7 Configuration Faults
27.7.1 Description
27.7.2 Specifications <\/td>\n<\/tr>\n
703<\/td>\n27.8 Enabling transport
27.8.1 Description
27.8.2 Specifications <\/td>\n<\/tr>\n
704<\/td>\n27.9 Transport Packet composition
27.9.1 Operations <\/td>\n<\/tr>\n
705<\/td>\n27.9.2 Directive, Register, and Data Elements
27.10 Directive Elements
27.10.1 Description
27.10.1.1 Overview <\/td>\n<\/tr>\n
706<\/td>\n27.10.1.2 Directive Element acronyms
27.10.1.3 Surrounding context of directives <\/td>\n<\/tr>\n
707<\/td>\n27.10.1.4 Directive\/transport building block relationships <\/td>\n<\/tr>\n
708<\/td>\n27.10.1.5 Directive encoding <\/td>\n<\/tr>\n
709<\/td>\n27.10.1.6 Directive types <\/td>\n<\/tr>\n
710<\/td>\n27.10.1.6.1 Unconditional Directives
27.10.1.6.2 Reset Directives
27.10.1.6.3 Selection Directives <\/td>\n<\/tr>\n
711<\/td>\n27.10.1.6.4 Conditional Directives <\/td>\n<\/tr>\n
712<\/td>\n27.10.1.6.5 Transfer Directives
27.10.2 Specifications <\/td>\n<\/tr>\n
716<\/td>\n27.11 Register Elements
27.11.1 Description
27.11.1.1 Overview
27.11.1.2 Register Element length
27.11.1.3 Transfer direction
27.11.1.4 Summary of Register Element characteristics <\/td>\n<\/tr>\n
717<\/td>\n27.11.2 Specifications
27.12 Data Elements
27.12.1 Description
27.12.1.1 Overview
27.12.1.2 Data Element length
27.12.1.3 Transfer direction <\/td>\n<\/tr>\n
718<\/td>\n27.12.1.4 Utilization and generation of data
27.12.1.5 Operation with single and multiple clients <\/td>\n<\/tr>\n
719<\/td>\n27.12.1.6 Summary of Data Element characteristics
27.12.2 Specifications <\/td>\n<\/tr>\n
720<\/td>\n27.13 Selection of control and data targets <\/td>\n<\/tr>\n
721<\/td>\n27.14 Data Channel Client functions
27.14.1 Description
27.14.1.1 Initializing a Data Channel Client
27.14.1.2 Orderly shutdown of a transfer <\/td>\n<\/tr>\n
722<\/td>\n27.14.1.3 Effects of Online\/Offline operation on the Transport Function <\/td>\n<\/tr>\n
723<\/td>\n27.14.2 Specifications
27.15 Partitioning of the Transport Control Function
27.15.1 Building blocks <\/td>\n<\/tr>\n
725<\/td>\n27.15.2 Directive\/register\/operational relationships <\/td>\n<\/tr>\n
726<\/td>\n27.16 Programming considerations
27.16.1 Managing transport with the DTS
27.16.2 Single and multi-client data exchanges
27.16.3 Bandwidth allocation
27.16.4 Common and uncommon operations performed with directives <\/td>\n<\/tr>\n
727<\/td>\n27.16.5 Dynamic source\/destination changes <\/td>\n<\/tr>\n
728<\/td>\n27.16.6 Transfer alignment characteristics
27.17 Aspects of transport not covered by this specification <\/td>\n<\/tr>\n
729<\/td>\n28. Transport operation and interfaces
28.1 Introduction
28.2 TAP interface
28.2.1 TPA state flow <\/td>\n<\/tr>\n
730<\/td>\n28.2.2 Directive Element characteristics
28.2.2.1 Description
28.2.2.2 Specifications <\/td>\n<\/tr>\n
732<\/td>\n28.2.3 Register Element characteristics
28.2.3.1 Description
28.2.3.1.1 Format, timing, and TMSC signal drive characteristics
28.2.3.1.2 Register Element length <\/td>\n<\/tr>\n
733<\/td>\n28.2.3.1.3 Register Element content <\/td>\n<\/tr>\n
734<\/td>\n28.2.3.2 Specifications <\/td>\n<\/tr>\n
735<\/td>\n28.2.4 Data Element characteristics
28.2.4.1 Description
28.2.4.1.1 Format, timing, and TMSC signal drive characteristics <\/td>\n<\/tr>\n
736<\/td>\n28.2.4.1.2 Data Element length <\/td>\n<\/tr>\n
737<\/td>\n28.2.4.1.3 Data Element content <\/td>\n<\/tr>\n
738<\/td>\n28.2.4.1.4 Drive characteristics
28.2.4.1.5 Multi-client data transfers <\/td>\n<\/tr>\n
739<\/td>\n28.2.4.1.6 Data Element alignment with the data that is transported
28.2.4.2 Specifications <\/td>\n<\/tr>\n
740<\/td>\n28.3 Transport State Machine
28.3.1 Description
28.3.1.1 Conceptual view <\/td>\n<\/tr>\n
742<\/td>\n28.3.1.2 TSM operation <\/td>\n<\/tr>\n
743<\/td>\n28.3.1.3 Scheduling a TP <\/td>\n<\/tr>\n
745<\/td>\n28.3.1.4 Starting\/restarting directive processing
28.3.1.5 Completing a TP <\/td>\n<\/tr>\n
746<\/td>\n28.3.2 Specifications <\/td>\n<\/tr>\n
747<\/td>\n28.4 PDCx\/DCC interface
28.4.1 Description <\/td>\n<\/tr>\n
748<\/td>\n28.4.1.1 Signal functions
28.4.1.2 Signal descriptions <\/td>\n<\/tr>\n
750<\/td>\n28.4.1.3 Signal use <\/td>\n<\/tr>\n
754<\/td>\n28.4.2 Specifications
28.5 Five-bit directives
28.5.1 Description
28.5.2 Specifications <\/td>\n<\/tr>\n
756<\/td>\n28.6 Eight-bit directives
28.6.1 Description <\/td>\n<\/tr>\n
757<\/td>\n28.6.2 Specifications <\/td>\n<\/tr>\n
758<\/td>\n28.7 12-bit directives
28.7.1 Description
28.7.2 Specifications <\/td>\n<\/tr>\n
761<\/td>\n28.8 DCC interface operation
28.8.1 Basic capability <\/td>\n<\/tr>\n
762<\/td>\n28.8.2 Pipelining register dcc_rdo signaling
28.8.3 Pipelining dcc_ddo and dcc_cor signaling <\/td>\n<\/tr>\n
763<\/td>\n28.9 An approach to implementing the Transport Function
28.9.1 Overview <\/td>\n<\/tr>\n
764<\/td>\n28.9.2 The Transport State Machine <\/td>\n<\/tr>\n
765<\/td>\n28.9.3 Multi-use register bits
28.9.3.1 Input configurations <\/td>\n<\/tr>\n
766<\/td>\n28.9.3.2 Transport Packet processing
28.9.3.2.1 Directive processing
28.9.3.2.2 Data Element processing <\/td>\n<\/tr>\n
767<\/td>\n28.9.3.2.3 12-bit directive processing (other than TP_CRR and TP_CRW)
28.9.3.2.4 TP_CRR and TP_CRW Directive processing <\/td>\n<\/tr>\n
768<\/td>\n28.9.3.3 TSM state\/register value relationships <\/td>\n<\/tr>\n
771<\/td>\n28.9.3.4 Transport output and DCR input selection <\/td>\n<\/tr>\n
773<\/td>\n28.9.3.5 TP activity examples <\/td>\n<\/tr>\n
778<\/td>\n29. Test concepts
29.1 Introduction
29.2 Interoperability <\/td>\n<\/tr>\n
779<\/td>\n29.3 Construction of the unit under test
29.4 Background (IEEE 1149.1 paradigm) <\/td>\n<\/tr>\n
780<\/td>\n29.4.1 Topology
29.4.2 Scan-state sequencing <\/td>\n<\/tr>\n
781<\/td>\n29.5 Implications for test applications arising from this standard
29.5.1 Divergences versus IEEE Std 1149.1 <\/td>\n<\/tr>\n
782<\/td>\n29.5.2 Accommodation\/resolution of divergences versus IEEE Std 1149.1
29.6 Test example\u2014a narrative <\/td>\n<\/tr>\n
783<\/td>\n29.7 Describing the unit under test <\/td>\n<\/tr>\n
784<\/td>\n29.8 Documentation model <\/td>\n<\/tr>\n
785<\/td>\n29.9 Considerations for large-system applications <\/td>\n<\/tr>\n
787<\/td>\n30. Documenting IEEE 1149.7 test endpoints (BSDL.7)
30.1 Introduction <\/td>\n<\/tr>\n
788<\/td>\n30.2 Conventions
30.3 Purpose of BSDL.7
30.4 Scope of BSDL.7 <\/td>\n<\/tr>\n
789<\/td>\n30.5 Expectations of a BSDL.7 parser
30.6 Relationship of BSDL.7 to BSDL.1
30.6.1 Description <\/td>\n<\/tr>\n
790<\/td>\n30.6.2 Specifications
30.7 Lexical elements of BSDL.7
30.7.1 Description
30.7.2 Specifications
30.8 BSDL.7 reserved words
30.8.1 Description
30.8.2 Specifications <\/td>\n<\/tr>\n
791<\/td>\n30.9 Components of a BSDL.7 description
30.9.1 Description
30.9.2 Specifications
30.10 The entity description (BSDL.7)
30.10.1 Overall structure of the entity description (BSDL.7)
30.10.1.1 Syntax and content
30.10.1.1.1 Description <\/td>\n<\/tr>\n
792<\/td>\n30.10.1.1.2 Specifications <\/td>\n<\/tr>\n
793<\/td>\n30.10.1.2 Semantic checks
30.10.1.2.1 Description
30.10.1.2.2 Specifications
30.10.2 Standard use statement (BSDL.7)
30.10.2.1 Syntax and content
30.10.2.1.1 Description <\/td>\n<\/tr>\n
794<\/td>\n30.10.2.1.2 Specifications
30.10.2.2 Examples <\/td>\n<\/tr>\n
795<\/td>\n30.10.3 Version control
30.10.3.1 Syntax and content
30.10.3.1.1 Description
30.10.3.1.2 Specifications
30.10.4 Component conformance statement (BSDL.7)
30.10.4.1 Syntax and content
30.10.4.1.1 Description <\/td>\n<\/tr>\n
796<\/td>\n30.10.4.1.2 Specifications
30.10.4.2 Examples
30.10.4.3 Semantic checks
30.10.5 Scan port identification (BSDL.7)
30.10.5.1 Syntax and content
30.10.5.1.1 Description <\/td>\n<\/tr>\n
797<\/td>\n30.10.5.1.2 Specifications
30.10.5.2 Examples <\/td>\n<\/tr>\n
799<\/td>\n30.10.5.3 Semantic checks
30.10.5.3.1 Description
30.10.5.3.2 Specifications <\/td>\n<\/tr>\n
800<\/td>\n30.10.6 Compliance enable description (BSDL.7)
30.10.6.1 Syntax and content
30.10.6.1.1 Description
30.10.6.1.2 Specifications
30.10.6.2 Examples <\/td>\n<\/tr>\n
801<\/td>\n30.10.6.3 Semantic checks
30.10.6.3.1 Description
30.10.6.3.2 Specifications
30.10.7 Device identification register description (BSDL.7)
30.10.7.1 Syntax and content
30.10.7.1.1 Description
30.10.7.1.2 Specifications
30.10.7.2 Examples <\/td>\n<\/tr>\n
802<\/td>\n30.10.7.3 Semantic checks
30.10.7.3.1 Description
30.10.7.3.2 Specifications
30.10.8 Configuration register description (BSDL.7)
30.10.8.1 Syntax and content
30.10.8.1.1 Description
30.10.8.1.2 Specifications
30.10.8.2 Examples <\/td>\n<\/tr>\n
803<\/td>\n30.10.8.3 Semantic checks
30.10.8.3.1 Description
30.10.8.3.2 Specifications <\/td>\n<\/tr>\n
804<\/td>\n30.11 The Standard BSDL.7 Package STD_1149_7_2009
30.11.1 Description
30.11.2 Specifications
30.12 A typical application of BSDL.7 <\/td>\n<\/tr>\n
807<\/td>\n31. Documenting IEEE 1149.7 test modules (HSDL.7)
31.1 Introduction
31.2 Conventions <\/td>\n<\/tr>\n
808<\/td>\n31.3 Purpose of HSDL.7
31.4 Scope of HSDL.7 <\/td>\n<\/tr>\n
809<\/td>\n31.5 Expectations of an HSDL.7 parser
31.6 Relationship of HSDL.7 to BSDL.7 (and BSDL.1)
31.6.1 Description <\/td>\n<\/tr>\n
810<\/td>\n31.6.2 Specifications
31.7 Lexical elements of HSDL.7
31.7.1 Description
31.7.2 Specifications
31.8 HSDL.7 reserved words
31.8.1 Description
31.8.2 Specifications
31.9 Components of an HSDL.7 description
31.9.1 Description <\/td>\n<\/tr>\n
811<\/td>\n31.9.2 Specifications
31.10 The entity description (HSDL.7)
31.10.1 Overall structure of the entity description (HSDL.7)
31.10.1.1 Syntax and content
31.10.1.1.1 Description
31.10.1.1.2 Specifications <\/td>\n<\/tr>\n
812<\/td>\n31.10.1.2 Semantic checks
31.10.1.2.1 Description
31.10.1.2.2 Specifications
31.10.2 Module standard use statement (HSDL.7)
31.10.2.1 Syntax and content
31.10.2.1.1 Description <\/td>\n<\/tr>\n
813<\/td>\n31.10.2.1.2 Specifications <\/td>\n<\/tr>\n
814<\/td>\n31.10.2.2 Examples
31.10.3 Version control
31.10.3.1 Syntax and content
31.10.3.1.1 Description
31.10.3.1.2 Specifications <\/td>\n<\/tr>\n
815<\/td>\n31.10.4 Module component conformance statement (HSDL.7)
31.10.4.1 Syntax and content
31.10.4.1.1 Description
31.10.4.1.2 Specifications
31.10.4.2 Examples
31.10.4.3 Semantic checks <\/td>\n<\/tr>\n
816<\/td>\n31.10.5 Module package pin mappings (HSDL.7)
31.10.5.1 Syntax and content
31.10.5.1.1 Description
31.10.5.1.2 Specifications
31.10.5.2 Examples
31.10.5.3 Semantic checks
31.10.5.3.1 Description
31.10.5.3.2 Specifications
31.10.6 Module scan port identification (HSDL.7)
31.10.6.1 Syntax and content
31.10.6.1.1 Description <\/td>\n<\/tr>\n
817<\/td>\n31.10.6.1.2 Specifications
31.10.6.2 Examples <\/td>\n<\/tr>\n
818<\/td>\n31.10.6.3 Semantic checks
31.10.6.3.1 Description
31.10.6.3.2 Specifications <\/td>\n<\/tr>\n
819<\/td>\n31.10.7 Module members declaration (HSDL.7)
31.10.7.1 Syntax and content
31.10.7.1.1 Description <\/td>\n<\/tr>\n
820<\/td>\n31.10.7.1.2 Specifications <\/td>\n<\/tr>\n
821<\/td>\n31.10.7.2 Examples <\/td>\n<\/tr>\n
822<\/td>\n31.10.7.3 Semantic checks
31.10.7.3.1 Description
31.10.7.3.2 Specifications <\/td>\n<\/tr>\n
823<\/td>\n31.11 The Standard HSDL.7 Package STD_1149_7_2009_module
31.11.1 Description
31.11.2 Specifications
31.12 Applications of HSDL.7
31.12.1 HSDL.7 for IEEE 1149.1 serial connection using one TMS signal <\/td>\n<\/tr>\n
825<\/td>\n31.12.2 HSDL.7 for IEEE 1149.1 connection in two paralleled serial chains <\/td>\n<\/tr>\n
826<\/td>\n31.12.3 HSDL.7 for a basic Star Scan Topology <\/td>\n<\/tr>\n
827<\/td>\n31.12.4 HSDL.7 for a basic hierarchical topology <\/td>\n<\/tr>\n
829<\/td>\n31.12.5 A typical application of HSDL.7 <\/td>\n<\/tr>\n
831<\/td>\nAnnex A (informative) IEEE 1149.1 reference material <\/td>\n<\/tr>\n
835<\/td>\nAnnex B (informative) Scan examples in timing diagram form
B.1 MScan and OScan SP types <\/td>\n<\/tr>\n
836<\/td>\nB.2 MScan and OScan transactions
B.2.1 MScan transaction <\/td>\n<\/tr>\n
838<\/td>\nB.2.2 OScan0 transaction <\/td>\n<\/tr>\n
839<\/td>\nB.2.3 OScan1 transaction <\/td>\n<\/tr>\n
840<\/td>\nB.2.4 OScan2 transaction <\/td>\n<\/tr>\n
841<\/td>\nB.2.5 OScan3 transaction <\/td>\n<\/tr>\n
842<\/td>\nB.2.6 OScan4 transaction <\/td>\n<\/tr>\n
843<\/td>\nB.2.7 OScan5 transaction <\/td>\n<\/tr>\n
844<\/td>\nB.2.8 OScan6 transaction <\/td>\n<\/tr>\n
846<\/td>\nB.2.9 OScan7 transaction <\/td>\n<\/tr>\n
847<\/td>\nB.3 SScan transactions <\/td>\n<\/tr>\n
848<\/td>\nB.3.1 SScan0 transaction <\/td>\n<\/tr>\n
851<\/td>\nB.3.2 SScan1 transaction <\/td>\n<\/tr>\n
854<\/td>\nB.3.3 SScan2 transaction <\/td>\n<\/tr>\n
857<\/td>\nB.3.4 SScan3 transaction <\/td>\n<\/tr>\n
860<\/td>\nB.4 BDX and CDX Transport Packet examples <\/td>\n<\/tr>\n
862<\/td>\nAnnex C (informative) Scan examples in tabular form
C.1 Overview
C.2 MScan and OScan SP types <\/td>\n<\/tr>\n
877<\/td>\nC.3 SScan SP types <\/td>\n<\/tr>\n
904<\/td>\nAnnex D (informative) Programming considerations
D.1 Overview
D.2 DTS\u2019 view of TAPs
D.2.1 Technology branches <\/td>\n<\/tr>\n
905<\/td>\nD.2.2 Power-management RSU combinations <\/td>\n<\/tr>\n
907<\/td>\nD.2.3 TAP.7 Controller deselection and selection <\/td>\n<\/tr>\n
908<\/td>\nD.2.4 Start-up versus steady-state operation <\/td>\n<\/tr>\n
909<\/td>\nD.2.5 Start-up <\/td>\n<\/tr>\n
910<\/td>\nD.2.6 Initialization requirements
D.2.6.1 Initial state
D.2.6.2 Factors influencing initialization
D.2.6.3 Initialization function <\/td>\n<\/tr>\n
911<\/td>\nD.2.6.4 Reset Escape <\/td>\n<\/tr>\n
912<\/td>\nD.2.6.5 Reset TAP.7 Controllers without an RSU
D.2.6.6 Power-up TAP.7 Controllers that are un-powered
D.2.6.7 Placing a TAP.7 Controller Online that is Offline-at-Start-up <\/td>\n<\/tr>\n
916<\/td>\nD.2.7 Scan Topology Training <\/td>\n<\/tr>\n
917<\/td>\nD.3 Scan topology interrogation <\/td>\n<\/tr>\n
918<\/td>\nD.3.1 Series Branch interrogation
D.3.1.1 Series characteristics used for interrogation <\/td>\n<\/tr>\n
919<\/td>\nD.3.1.2 Interrogation process <\/td>\n<\/tr>\n
921<\/td>\nD.3.1.3 Configuration Register reads <\/td>\n<\/tr>\n
922<\/td>\nD.3.1.4 Determining whether a Series Branch is selectable
D.3.1.5 Quick determination of TAP types in a Series Branch <\/td>\n<\/tr>\n
923<\/td>\nD.3.2 Star-4 Branch interrogation
D.3.2.1 Information provided
D.3.2.2 Interrogation process <\/td>\n<\/tr>\n
927<\/td>\nD.3.3 Star-2 Branch interrogation
D.3.3.1 Information provided
D.3.3.2 Interrogation process <\/td>\n<\/tr>\n
930<\/td>\nD.4 Establishing TAP.7 operating conditions
D.5 CID management <\/td>\n<\/tr>\n
931<\/td>\nD.6 Managing simultaneous debug actions
D.7 Operations to avoid with a Star-4 Scan Topology
D.7.1 The use of the JScan0\u2013JScan2 Scan Formats
D.7.2 The selection of CLTAPCs of TAP.7 Controllers allocated the same CID <\/td>\n<\/tr>\n
932<\/td>\nD.8 Using a T5 TAP.7
D.8.1 Setup and use of the Transport Function
D.8.2 Sharing the use of a Logical Data Channel
D.8.3 Transferring data with Transport Packet Data Payloads <\/td>\n<\/tr>\n
933<\/td>\nAnnex E (informative) Recommended electrical characteristics <\/td>\n<\/tr>\n
934<\/td>\nAnnex F (informative) Connectivity\/electrical recommendations
F.1 Overview
F.1.1 General information
F.1.2 Factors affecting reliable operation <\/td>\n<\/tr>\n
935<\/td>\nF.1.3 Factors affecting link performance <\/td>\n<\/tr>\n
936<\/td>\nF.2 Physical connection topologies considered <\/td>\n<\/tr>\n
937<\/td>\nF.3 Termination schemes considered <\/td>\n<\/tr>\n
939<\/td>\nF.4 Chip considerations
F.4.1 SOC input conditioning <\/td>\n<\/tr>\n
940<\/td>\nF.4.2 Signal driver rise and fall times <\/td>\n<\/tr>\n
942<\/td>\nF.4.3 Clock-to-output delays
F.4.4 Supply and buffer impedances
F.4.5 Additional chip considerations related to multi-TAPC topologies
F.5 Board considerations
F.5.1 Signaling requiring a termination scheme <\/td>\n<\/tr>\n
943<\/td>\nF.5.1.1 Lumped load
F.5.1.2 Distributed load
F.5.1.3 Classifying a load <\/td>\n<\/tr>\n
944<\/td>\nF.5.1.4 Transmission-line impedance <\/td>\n<\/tr>\n
945<\/td>\nF.5.2 Impedance discontinuities\/symmetry <\/td>\n<\/tr>\n
948<\/td>\nF.5.3 Transmission-line construction
F.5.3.1 Uniformity of transmission-line impedance
F.5.3.2 Proper construction <\/td>\n<\/tr>\n
950<\/td>\nF.5.3.3 Improper construction
F.5.3.4 Connector treatment
F.5.4 Choosing a connection configuration <\/td>\n<\/tr>\n
951<\/td>\nF.5.5 Termination schemes with simple configurations
F.5.5.1 Series termination
F.5.5.1.1 Overview <\/td>\n<\/tr>\n
952<\/td>\nF.5.5.1.2 Challenges in series termination
F.5.5.1.3 Benefits of using series termination
F.5.5.2 Parallel termination
F.5.5.2.1 Overview <\/td>\n<\/tr>\n
954<\/td>\nF.5.5.2.2 Challenges in using parallel termination <\/td>\n<\/tr>\n
955<\/td>\nF.5.5.2.3 Benefits of using parallel termination
F.5.5.3 Parallel AC termination
F.5.5.3.1 Overview <\/td>\n<\/tr>\n
957<\/td>\nF.5.5.3.2 Challenges in using parallel AC termination <\/td>\n<\/tr>\n
958<\/td>\nF.5.5.3.3 Benefits of using parallel AC termination
F.5.6 Effects of transmission-line length on operating frequency <\/td>\n<\/tr>\n
959<\/td>\nF.5.7 Capacitive load isolation and input pin low-pass filtering
F.5.8 DTS and chip models <\/td>\n<\/tr>\n
960<\/td>\nF.5.9 Additional board considerations related to multi-TAPC topologies
F.6 System considerations for supporting Keeper bias (K bias) in multi-TAPC topologies
F.6.1 K bias considerations at the chip and board level <\/td>\n<\/tr>\n
962<\/td>\nF.6.2 K bias considerations for embedded TAPC topologies <\/td>\n<\/tr>\n
964<\/td>\nF.7 DTS considerations
F.7.1 Source impedance <\/td>\n<\/tr>\n
965<\/td>\nF.7.2 Input capacitance isolation
F.7.2.1 DTS output levels with parallel terminated target topologies
F.7.2.2 DTS output edge rates <\/td>\n<\/tr>\n
966<\/td>\nF.7.2.3 High-speed, high-current, low-voltage configurable edge-rate drivers
F.7.2.4 Low-voltage, high-current fixed slow edge-rate drive translator <\/td>\n<\/tr>\n
968<\/td>\nF.7.2.5 In-system DTS considerations
F.7.2.5.1 Output buffer impedance
F.7.2.5.2 Power considerations
F.7.2.5.3 Signal edge rates
F.8 Point-to-Point configuration
F.8.1 Model <\/td>\n<\/tr>\n
969<\/td>\nF.8.2 Unidirectional signaling
F.8.2.1 Series termination
F.8.2.2 Parallel AC termination <\/td>\n<\/tr>\n
970<\/td>\nF.8.3 Bidirectional signaling <\/td>\n<\/tr>\n
972<\/td>\nF.9 Line configuration of a transmission line
F.9.1 Model <\/td>\n<\/tr>\n
974<\/td>\nF.9.2 Unidirectional signaling <\/td>\n<\/tr>\n
979<\/td>\nF.9.2.1 Parallel AC termination <\/td>\n<\/tr>\n
981<\/td>\nF.9.2.2 Parallel termination
F.9.2.3 Summary
F.9.3 Bidirectional signaling <\/td>\n<\/tr>\n
984<\/td>\nF.9.3.1 Four loads <\/td>\n<\/tr>\n
987<\/td>\nF.9.3.2 Eight loads <\/td>\n<\/tr>\n
990<\/td>\nF.10 T configuration of a transmission line
F.10.1 Model <\/td>\n<\/tr>\n
993<\/td>\nF.10.2 Unidirectional signaling <\/td>\n<\/tr>\n
994<\/td>\nF.10.3 Bidirectional signaling <\/td>\n<\/tr>\n
998<\/td>\nF.11 X configuration of a transmission line
F.11.1 Model <\/td>\n<\/tr>\n
1000<\/td>\nF.11.2 Unidirectional signaling <\/td>\n<\/tr>\n
1003<\/td>\nF.11.3 Bidirectional signaling <\/td>\n<\/tr>\n
1009<\/td>\nF.12 XT configuration of a transmission line
F.12.1 Model <\/td>\n<\/tr>\n
1010<\/td>\nF.12.2 Unidirectional signaling <\/td>\n<\/tr>\n
1012<\/td>\nF.12.3 Bidirectional signaling <\/td>\n<\/tr>\n
1018<\/td>\nF.13 Recommendations
F.13.1 Summary <\/td>\n<\/tr>\n
1019<\/td>\nF.13.2 Connectivity\/termination scheme <\/td>\n<\/tr>\n
1021<\/td>\nF.13.3 Termination scheme\/capacitive load isolation\/signal relationships <\/td>\n<\/tr>\n
1023<\/td>\nF.13.4 Utilizing board design tools and simulation <\/td>\n<\/tr>\n
1024<\/td>\nAnnex G (informative) Utilizing SScan Scan Formats <\/td>\n<\/tr>\n
1028<\/td>\nAnnex H (informative) The RTCK signal <\/td>\n<\/tr>\n
1036<\/td>\nAnnex I (informative) Bibliography <\/td>\n<\/tr>\n
1037<\/td>\nIndex <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":"

IEEE Standard for Reduced-Pin and Enhanced-Functionality Test Access Port and Boundary-Scan Architecture<\/b><\/p>\n\n\n\n\n
Published By<\/td>\nPublication Date<\/td>\nNumber of Pages<\/td>\n<\/tr>\n
IEEE<\/b><\/a><\/td>\n2022<\/td>\n<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n","protected":false},"featured_media":125388,"template":"","meta":{"rank_math_lock_modified_date":false,"ep_exclude_from_search":false},"product_cat":[2644],"product_tag":[],"class_list":{"0":"post-125387","1":"product","2":"type-product","3":"status-publish","4":"has-post-thumbnail","6":"product_cat-ieee","8":"first","9":"instock","10":"sold-individually","11":"shipping-taxable","12":"purchasable","13":"product-type-simple"},"_links":{"self":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product\/125387","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product"}],"about":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/types\/product"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media\/125388"}],"wp:attachment":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media?parent=125387"}],"wp:term":[{"taxonomy":"product_cat","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_cat?post=125387"},{"taxonomy":"product_tag","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_tag?post=125387"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}