IEEE 802.3ba-2010

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IEEE Standard for Information technology– Local and metropolitan area networks– Specific requirements– Part 3: CSMA/CD Access Method and Physical Layer Specifications Amendment 4: Media Access Control Parameters, Physical Layers, and Management Parameters for 40 Gb/s and 100 Gb/s Operation

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IEEE	2010	457

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Description

Amendment Standard – Superseded. This amendment to IEEE Std 802.3-2008 includes changes to IEEE Std 802.3-2008 and adds Clause 80 through Clause 88, Annex 83A through Annex 83C, Annex 85A, and Annex 86A. This amendment includes IEEE 802.3 Media Access Control (MAC) parameters, Physical Layer specifications, and management parameters for the transfer of IEEE 802.3 format frames at 40 Gb/s and 100 Gb/s.

PDF Catalog

PDF Pages	PDF Title
1	IEEE Std 802.3ba-2010 Cover page
3	Title page
6	Introduction
7	Notice to users Laws and regulations Copyrights
8	Updating of IEEE documents Errata Interpretations Patents
9	Participants David J. Law, IEEE 802.3 Working Group Chair Wael William Diab, IEEE 802.3 Working Group Vice-Chair Steven B. Carlson, IEEE 802.3 Working Group Executive Secretary Adam Healey, IEEE 802.3 Working Group Secretary Bradley Booth, IEEE 802.3 Working Grou…
12	Robert M. Grow, Chair Richard H. Hulett, Vice Chair Steve M. Mills, Past Chair
15	Contents
25	Important Notice
26	1. Introduction 1.1.3.2 Compatibility interfaces 1.2.3 Physical Layer and media notation
27	1.3 Normative references
28	1.4 Definitions
29	1.5 Abbreviations
31	4. Media Access Control 4.4.2 MAC parameters
33	30. Management 30.3.2.1.2 aPhyType 30.3.2.1.3 aPhyTypeList
34	30.3.2.1.5 aSymbolErrorDuringCarrier 30.5.1.1.2 aMAUType
35	30.5.1.1.4 aMediaAvailable
36	30.5.1.1.10a aBIPErrorCount
37	30.5.1.1.10b aLaneMapping 30.5.1.1.14 aFECmode 30.5.1.1.15 aFECCorrectedBlocks
38	30.5.1.1.16 aFECUncorrectableBlocks 30.6.1.1.5 aAutoNegLocalTechnologyAbility
41	45. Management Data Input/Output (MDIO) Interface 45.2 MDIO Interface Registers 45.2.1 PMA/PMD registers
43	45.2.1.1 PMA/PMD control 1 register (Register 1.0) 45.2.1.1.3 Speed selection (1.0.13,1.0.6, 1.0.5:2)
45	45.2.1.1.3a PMA remote loopback (1.0.1) 45.2.1.1.4 PMA local loopback (1.0.0)
46	45.2.1.2.1 Fault (1.1.7) 45.2.1.4.a 100G capable (1.4.9) 45.2.1.4.b 40G capable (1.4.8)
48	45.2.1.6.1 PMA/PMD type selection (1.7.35:0) 45.2.1.7 10G PMA/PMD status 2 register (Register 1.8) 45.2.1.7.4 Transmit fault (1.8.11)
49	45.2.1.7.5 Receive fault (1.8.10) 45.2.1.7.15 PMA local loopback ability (1.8.0) 45.2.1.8 10G PMD transmit disable register (Register 1.9)
50	45.2.1.8.a PMD transmit disable 9 (1.9.10) 45.2.1.8.b PMD transmit disable 4, 5, 6, 7, 8 (1.9.5, 1.9.6, 1.9.7, 1.9.8, 1.9.9) 45.2.1.9 10G PMD receive signal detect register (Register 1.10)
51	45.2.1.9.a PMD receive signal detect 9 (1.10.10) 45.2.1.9.b PMD receive signal detect 4, 5, 6, 7, 8 (1.10.5, 1.10.6, 1.10.7, 1.10.8, 1.10.9)
52	45.2.1.10 PMA/PMD extended ability register (Register 1.11) 45.2.1.11a 40G/100G PMA/PMD extended ability register (Register 1.13)
53	45.2.1.11a.1 PMA remote loopback ability (1.13.15) 45.2.1.11a.2 100GBASE-ER4 ability (1.13.11) 45.2.1.11a.3 100GBASE-LR4 ability (1.13.10) 45.2.1.11a.4 100GBASE-SR10 ability (1.13.9) 45.2.1.11a.5 100GBASE-CR10 ability (1.13.8) 45.2.1.11a.6 40GBASE-LR4 ability (1.13.3) 45.2.1.11a.7 40GBASE-SR4 ability (1.13.2) 45.2.1.11a.8 40GBASE-CR4 ability (1.13.1) 45.2.1.11a.9 40GBASE-KR4 ability (1.13.0)
54	45.2.1.77 10GBASE-KR BASE-R PMD control register (Register 1.150) 45.2.1.78 10GBASE-KR BASE-R PMD status register (Register 1.151)
55	45.2.1.78.1 Receiver status 0 (1.151.0) 45.2.1.78.2 Frame lock 0 (1.151.1) 45.2.1.78.3 Start-up protocol status 0 (1.151.2) 45.2.1.78.4 Training failure 0 (1.151.3) 45.2.1.78.5 Receiver status 1, 2, 3 (1.151.4, 1.151.8, 1.151.12) 45.2.1.78.6 Frame lock 1, 2, 3 (1.151.5, 1.151.9, 1.151.13) 45.2.1.78.7 Start-up protocol status 1, 2, 3 (1.151.6, 1.151.10, 1.151.14)
56	45.2.1.78.8 Training failure 1, 2, 3 (1.151.7, 1.151.11, 1.151.15) 45.2.1.79 10GBASE-KR BASE-R LP coefficient update, lane 0 register (Register 1.152) 45.2.1.80 10GBASE-KR BASE-R LP status report, lane 0 register (Register 1.153)
57	45.2.1.81 10GBASE-KR BASE-R LD coefficient update, lane 0 register (Register 1.154) 45.2.1.82 10GBASE-KR BASE-R LD status report, lane 0 register (Register 1.155)
58	45.2.1.82a BASE-R PMD status 2 register (Register 1.156)
59	45.2.1.82a.1 Receiver status 4, 5, 6, 7 (1.156.0, 1.156.4, 1.156.8, 1.156.12) 45.2.1.82a.2 Frame lock 4, 5, 6, 7 (1.156.1, 1.156.5, 1.156.9, 1.156.13) 45.2.1.82a.3 Start-up protocol status 4, 5, 6, 7 (1.156.2, 1.156.6, 1.156.10, 1.156.14) 45.2.1.82a.4 Training failure 4, 5, 6, 7 (1.156.3, 1.156.7, 1.156.11, 1.156.15) 45.2.1.82b BASE-R PMD status 3 register (Register 1.157) 45.2.1.82b.1 Receiver status 8, 9 (1.157.0, 1.157.4)
60	45.2.1.82b.2 Frame lock 8, 9 (1.157.1, 1.157.5) 45.2.1.82b.3 Start-up protocol status 8, 9 (1.157.2, 1.157.6) 45.2.1.82b.4 Training failure 8, 9 (1.157.3, 1.157.7) 45.2.1.85 10GBASE-R FEC ability register (Register 1.170) 45.2.1.85.1 10GBASE-R FEC ability (1.170.0) 45.2.1.85.2 10GBASE-R FEC error indication ability (1.170.1)
61	45.2.1.86 10GBASE-R FEC control register (Register 1.171) 45.2.1.86.1 FEC enable (1.171.0) 45.2.1.86.2 FEC enable error indication (1.171.1) 45.2.1.87 10GBASE-R FEC corrected blocks counter (Register 1.172, 1.173)
62	45.2.1.88 10GBASE-R FEC uncorrected blocks counter (Register 1.174, 1.175) 45.2.1.89 BASE-R FEC corrected blocks counter, lanes 0 through 19
63	45.2.1.90 BASE-R FEC uncorrected blocks counter, lanes 0 through 19 45.2.1.91 BASE-R LP coefficient update register, lanes 1 through 9 45.2.1.92 BASE-R LP status report register, lanes 1 through 9 45.2.1.93 BASE-R LD coefficient update register, lanes 1 through 9 45.2.1.94 BASE-R LD status report register, lanes 1 through 9
64	45.2.1.95 Test-pattern ability (Register 1.1500)
65	45.2.1.96 PRBS pattern testing control (Register 1.1501)
66	45.2.1.97 Square wave testing control (Register 1.1510) 45.2.1.98 PRBS Tx pattern testing error counter (Register 1.1600, 1.1601, 1.1602, 1.1603, 1.1604, 1.1605, 1.1606, 1.1607, 1.1608, 1.1609)
67	45.2.1.99 PRBS Rx pattern testing error counter (Register 1.1700, 1.1701, 1.1702, 1.1703, 1.1704, 1.1705, 1.1706, 1.1707, 1.1708, 1.1709)
68	45.2.3 PCS registers
69	45.2.3.2.2 PCS receive link status (3.1.2) 45.2.3.4.3 40G capable (3.4.2)
70	45.2.3.4.4 100G capable (3.4.3) 45.2.3.6 10G PCS control 2 register (Register 3.7) 45.2.3.6.1 PCS type selection (3.7.12:0) 45.2.3.7 10G PCS status 2 register (Register 3.8) 45.2.3.7.3a 100GBASE-R capable (3.8.5)
71	45.2.3.7.3b 40GBASE-R capable (3.8.4) 45.2.3.11 10GBASE-R PCS and 10GBASE-T PCS status 1 register (Register 3.32) 45.2.3.11.1 10GBASE-R and 10GBASE-T receive link status (3.32.12) 45.2.3.11.4 10GBASE-R and 10GBASE-T PCS high BER (3.32.1)
72	45.2.3.11.5 10GBASE-R and 10GBASE-T PCS block lock (3.32.0) 45.2.3.12 10GBASE-R and 10GBASE-T PCS status 2 register (Register 3.33)
73	45.2.3.12.1 Latched block lock (3.33.15) 45.2.3.12.2 Latched high BER (3.33.14) 45.2.3.12.3 BER (3.33.13:8) 45.2.3.12.4 Errored blocks (3.33.7:0)
74	45.2.3.15 10GBASE-R PCS test-pattern control register (Register 3.42) 45.2.3.15.a Scrambled idle test-pattern enable (3.42.7)
75	45.2.3.15.1 10GBASE-R PRBS9 transmit test-pattern enable (3.42.6) 45.2.3.15.2 10GBASE-R PRBS31 receive test-pattern enable (3.42.5) 45.2.3.15.3 10GBASE-R PRBS31 transmit test-pattern enable (3.42.4) 45.2.3.16 10GBASE-R PCS test-pattern error counter register (Register 3.43) 45.2.3.16a BER high order counter (Register 3.44)
76	45.2.3.16b Errored blocks high order counter (Register 3.45) 45.2.3.16c Multi-lane BASE-R PCS alignment status 1 register (Register 3.50) 45.2.3.16c.1 Multi-lane BASE-R PCS alignment status (3.50.12) 45.2.3.16c.2 Block 7 lock (3.50.7) 45.2.3.16c.3 Block 6 lock (3.50.6)
77	45.2.3.16c.4 Block 5 lock (3.50.5) 45.2.3.16c.5 Block 4 lock (3.50.4) 45.2.3.16c.6 Block 3 lock (3.50.3)
78	45.2.3.16c.7 Block 2 lock (3.50.2) 45.2.3.16c.8 Block 1 lock (3.50.1) 45.2.3.16c.9 Block 0 lock (3.50.0) 45.2.3.16d Multi-lane BASE-R PCS alignment status 2 register (Register 3.51) 45.2.3.16d.1 Block 19 lock (3.51.11) 45.2.3.16d.2 Block 18 lock (3.51.10) 45.2.3.16d.3 Block 17 lock (3.51.9) 45.2.3.16d.4 Block 16 lock (3.51.8)
79	45.2.3.16d.5 Block 15 lock (3.51.7) 45.2.3.16d.6 Block 14 lock (3.51.6)
80	45.2.3.16d.7 Block 13 lock (3.51.5) 45.2.3.16d.8 Block 12 lock (3.51.4) 45.2.3.16d.9 Block 11 lock (3.51.3) 45.2.3.16d.10 Block 10 lock (3.51.2) 45.2.3.16d.11 Block 9 lock (3.51.1) 45.2.3.16d.12 Block 8 lock (3.51.0) 45.2.3.16e Multi-lane BASE-R PCS alignment status 3 register (Register 3.52) 45.2.3.16e.1 Lane 7 aligned (3.52.7)
81	45.2.3.16e.2 Lane 6 aligned (3.52.6) 45.2.3.16e.3 Lane 5 aligned (3.52.5) 45.2.3.16e.4 Lane 4 aligned (3.52.4) 45.2.3.16e.5 Lane 3 aligned (3.52.3)
82	45.2.3.16e.6 Lane 2 aligned (3.52.2) 45.2.3.16e.7 Lane 1 aligned (3.52.1) 45.2.3.16e.8 Lane 0 aligned (3.52.0) 45.2.3.16f Multi-lane BASE-R PCS alignment status 4 register (Register 3.53) 45.2.3.16f.1 Lane 19 aligned (3.53.11) 45.2.3.16f.2 Lane 18 aligned (3.53.10) 45.2.3.16f.3 Lane 17 aligned (3.53.9) 45.2.3.16f.4 Lane 16 aligned (3.53.8)
83	45.2.3.16f.5 Lane 15 aligned (3.53.7) 45.2.3.16f.6 Lane 14 aligned (3.53.6)
84	45.2.3.16f.7 Lane 13 aligned (3.53.5) 45.2.3.16f.8 Lane 12 aligned (3.53.4) 45.2.3.16f.9 Lane 11 aligned (3.53.3) 45.2.3.16f.10 Lane 10 aligned (3.53.2) 45.2.3.16f.11 Lane 9 aligned (3.53.1) 45.2.3.16f.12 Lane 8 aligned (3.53.0) 45.2.3.36 BIP error counter lane 0 (Register 3.200)
85	45.2.3.37 BIP error counter, lanes 1 through 19 (Registers 3.201 through 3.219) 45.2.3.38 Lane 0 mapping register (Register 3.400) 45.2.3.39 Lanes 1 through 19 mapping registers (Registers 3.401 through 3.419)
86	45.2.7 Auto-Negotiation registers 45.2.7.12 Backplane Ethernet, BASE-R copper status (Register 7.48)
87	45.2.7.12.1 10GBASE-KR BASE-R FEC negotiated (7.48.4) 45.2.7.12.2 Negotiated Port Type (7.48.1, 7.48.2, 7.48.3, 7.48.5, 7.48.6, 7.48.8) 45.2.7.12.3 Backplane Ethernet, BASE-R copper AN ability (7.48.0)
88	45.5 Protocol implementation conformance statement (PICS) proforma for Clause 45, MDIO interface 45.5.3.2 PMA/PMD MMD options
90	45.5.3.3 PMA/PMD management functions
92	45.5.3.6 PCS options
93	45.5.3.7 PCS management functions
95	52. Physical Medium Dependent (PMD) sublayer and baseband medium, type 10GBASE-S (short wavelength serial), 10GBASE-L (long wavelength serial), and 10GBASE-E (extra long wavelength serial) 52.9.10 Transmitter and dispersion penalty measurement
97	69. Introduction to Ethernet operation over electrical backplanes 69.1 Overview 69.1.1 Scope 69.1.2 Objectives 69.1.3 Relationship of Backplane Ethernet to the ISO OSI reference model
98	69.2 Summary of Backplane Ethernet Sublayers 69.2.1 Reconciliation Sublayer and media independent interfaces
99	69.2.3 Physical Layer signaling systems 69.2.5 Management 69.3 Delay constraints
101	73. Auto-Negotiation for backplane and copper cable assembly 73.2 Relationship to the ISO/IEC Open Systems Interconnection (OSI) reference model 73.3 Functional specifications
102	73.5 DME transmission 73.5.1 DME page encoding electrical specifications 73.5.1.1 DME electrical specifications
103	73.6 Link codeword encoding 73.6.4 Technology Ability Field 73.6.5 FEC capability
104	73.7 Receive function requirements 73.7.1 DME page reception 73.7.2 Receive Switch function 73.7.4.1 Parallel Detection function
105	73.7.6 Priority Resolution function 73.10 State diagrams and variable definitions 73.10.1 State diagram variables
106	73.10.2 State diagram timers
108	73.11 Protocol implementation conformance statement (PICS) proforma for Clause 73, Auto-Negotiation for Bbackplane Ethernet and copper cable assembly 73.11.1 Introduction 73.11.2.2 Protocol summary 73.11.4 PICS proforma tables for Auto-Negotiation for backplane and copper cable assembly 73.11.4.2 DME transmission
109	73.11.4.3 Link codeword encoding 73.11.4.7 State diagrams and variable definitions
111	74. Forward Error Correction (FEC) sublayer for 10GBASE-R PHYs 74.1 Overview 74.2 Objectives 74.3 Relationship to other sublayers
112	74.4 Inter-sublayer interfaces
113	74.4.1 Functional block diagram for 10GBASE-R PHYs 74.4.2 Functional block diagram for 40GBASE-R PHYs
114	74.4.3 Functional block diagram for 100GBASE-R PHYs
115	74.5 FEC service interface
116	74.5.1 10GBASE-R service primitives 74.5.1.1 FEC_UNITDATA.request 74.5.1.1.1 Semantics of the service primitive 74.5.1.1.2 When generated 74.5.1.1.3 Effect of receipt 74.5.1.2 FEC_UNITDATA.indication 74.5.1.2.1 Semantics of the service primitive
117	74.5.1.2.2 When generated 74.5.1.2.3 Effect of receipt 74.5.1.3 FEC_SIGNAL.indication 74.5.1.3.1 Semantics of the service primitive 74.5.1.3.2 When generated 74.5.1.3.3 Effect of receipt 74.5.2 40GBASE-R and 100GBASE-R service primitives
118	74.6 Delay constraints 74.7 FEC principle of operation
119	74.7.3 Composition of the FEC block 74.7.4.1 Reverse gearbox function 74.7.4.1.1 Reverse gearbox function for 10GBASE-R 74.7.4.1.2 Reverse gearbox function for 40GBASE-R and 100GBASE-R
121	74.7.4.3 FEC transmission bit ordering
122	74.7.4.4 FEC (2112, 2080) encoder 74.7.4.5 FEC decoder
123	74.7.4.5.1 FEC (2112,2080) decoding
125	74.7.4.6 FEC receive bit ordering
126	74.8 FEC MDIO function mapping 74.8.1 FEC capability
127	74.8.2 FEC enable 74.8.3 FEC Enable Error Indication 74.8.3.1 FEC Error Indication ability 74.8.4.1 FEC_corrected_blocks_counter
128	74.8.4.2 FEC_uncorrected_blocks_counter 74.9 BASE-R PHY test-pattern mode 74.10.2.2 Variables
129	74.11 Protocol implementation conformance statement (PICS) proforma for Clause 74, Forward Error Correction (FEC) sublayer for 10GBASE-R PHYs 74.11.1 Introduction 74.11.2.2 Protocol summary
130	74.11.3 Major capabilities/options 74.11.5 FEC requirements
131	80. Introduction to 40 Gb/s and 100 Gb/s networks 80.1 Overview 80.1.1 Scope 80.1.2 Objectives 80.1.3 Relationship of 40 Gigabit and 100 Gigabit Ethernet to the ISO OSI reference model
133	80.1.4 Nomenclature 80.1.5 Physical Layer signaling systems
134	80.2 Summary of 40 Gigabit and 100 Gigabit Ethernet sublayers 80.2.1 Reconciliation Sublayer (RS) and Media Independent Interface 80.2.2 Physical Coding Sublayer (PCS)
135	80.2.3 Forward Error Correction (FEC) sublayer 80.2.4 Physical Medium Attachment (PMA) sublayer 80.2.5 Physical Medium Dependent (PMD) sublayer 80.2.6 Auto-Negotiation 80.2.7 Management interface (MDIO/MDC) 80.2.8 Management
136	80.3 Service interface specification method and notation 80.3.1 Inter-sublayer service interface 80.3.2 Instances of the Inter-sublayer service interface
139	80.3.3 Semantics of inter-sublayer service interface primitives 80.3.3.1 IS_UNITDATA_i.request 80.3.3.1.1 Semantics of the service primitive 80.3.3.1.2 When generated 80.3.3.1.3 Effect of receipt 80.3.3.2 IS_UNITDATA_i.indication 80.3.3.2.1 Semantics of the service primitive
140	80.3.3.2.2 When generated 80.3.3.2.3 Effect of receipt 80.3.3.3 IS_SIGNAL.indication 80.3.3.3.1 Semantics of the service primitive 80.3.3.3.2 When generated 80.3.3.3.3 Effect of receipt 80.4 Delay constraints
141	80.5 Skew constraints
145	80.6 State diagrams 80.7 Protocol implementation conformance statement (PICS) proforma
147	81. Reconciliation Sublayer (RS) and Media Independent Interface for 40 Gb/s and 100 Gb/s operation (XLGMII and CGMII) 81.1 Overview
148	81.1.1 Summary of major concepts 81.1.2 Application 81.1.3 Rate of operation 81.1.4 Delay constraints
149	81.1.5 Allocation of functions 81.1.6 XLGMII/CGMII structure
150	81.1.7 Mapping of XLGMII/CGMII signals to PLS service primitives 81.1.7.1 Mapping of PLS_DATA.request 81.1.7.1.1 Function 81.1.7.1.2 Semantics of the service primitive 81.1.7.1.3 When generated 81.1.7.1.4 Effect of receipt
151	81.1.7.2 Mapping of PLS_DATA.indication 81.1.7.2.1 Function 81.1.7.2.2 Semantics of the service primitive 81.1.7.2.3 When generated 81.1.7.2.4 Effect of receipt 81.1.7.3 Mapping of PLS_CARRIER.indication 81.1.7.4 Mapping of PLS_SIGNAL.indication 81.1.7.5 Mapping of PLS_DATA_VALID.indication 81.1.7.5.1 Function 81.1.7.5.2 Semantics of the service primitive
152	81.1.7.5.3 When generated 81.1.7.5.4 Effect of receipt 81.2 XLGMII/CGMII data stream
153	81.2.1 Inter-frame 81.2.2 Preamble and start of frame delimiter
154	81.2.3 Data 81.2.4 End of frame delimiter 81.2.5 Definition of Start of Packet and End of Packet Delimiters 81.3 XLGMII/CGMII functional specifications 81.3.1 Transmit 81.3.1.1 TX_CLK
155	81.3.1.2 TXC (transmit control) 81.3.1.3 TXD (transmit data)
157	81.3.1.4 Start control character alignment
158	81.3.2 Receive 81.3.2.1 RX_CLK (receive clock) 81.3.2.2 RXC (receive control)
160	81.3.2.3 RXD (receive data)
161	81.3.3 Error and fault handling 81.3.3.1 Response to error indications by the XLGMII/CGMII
162	81.3.3.2 Conditions for generation of transmit Error control characters 81.3.3.3 Response to received invalid frame sequences 81.3.4 Link fault signaling
163	81.3.4.1 Variables and counters 81.3.4.2 State Diagram
165	81.4 Protocol implementation conformance statement (PICS) proforma for Clause 81, Reconciliation Sublayer (RS) and Media Independent Interface for 40 Gb/s and 100 Gb/s operation 81.4.1 Introduction 81.4.2 Identification 81.4.2.1 Implementation identification 81.4.2.2 Protocol summary
166	81.4.2.3 Major capabilities/options 81.4.3 PICS proforma tables for Reconciliation Sublayer and Media Independent Interface for 40 Gb/s and 100 Gb/s operation 81.4.3.1 General 81.4.3.2 Mapping of PLS service primitives
167	81.4.3.3 Data stream structure
168	81.4.3.4 XLGMII/CGMII signal functional specifications
169	81.4.3.5 Link fault signaling state diagram
171	82. Physical Coding Sublayer (PCS) for 64B/66B, type 40GBASE-R and 100GBASE-R 82.1 Overview 82.1.1 Scope 82.1.2 Relationship of 40GBASE-R and 100GBASE-R to other standards
172	82.1.3 Summary of 40GBASE-R and 100GBASE-R sublayers 82.1.3.1 Physical Coding Sublayer (PCS)
173	82.1.4 Inter-sublayer interfaces 82.1.4.1 PCS service interface (XLGMII/CGMII) 82.1.4.2 Physical Medium Attachment (PMA) service interface 82.1.5 Functional block diagram
174	82.2 Physical Coding Sublayer (PCS) 82.2.1 Functions within the PCS
175	82.2.2 Use of blocks
176	82.2.3 64B/66B transmission code 82.2.3.1 Notation conventions 82.2.3.2 Transmission order
179	82.2.3.3 Block structure
180	82.2.3.4 Control codes
181	82.2.3.5 Valid and invalid blocks 82.2.3.6 Idle (/I/) 82.2.3.7 Start (/S/) 82.2.3.8 Terminate (/T/)
182	82.2.3.9 ordered_set (/O/) 82.2.3.10 Error (/E/) 82.2.4 Transmit process 82.2.5 Scrambler 82.2.6 Block distribution
183	82.2.7 Alignment marker insertion
185	82.2.8 BIP calculations
186	82.2.9 PMA or FEC Interface
187	82.2.10 Test-pattern generators 82.2.11 Block synchronization 82.2.12 PCS lane deskew 82.2.13 PCS lane reorder
188	82.2.14 Alignment marker removal 82.2.15 Descrambler 82.2.16 Receive process 82.2.17 Test-pattern checker
189	82.2.18 Detailed functions and state diagrams 82.2.18.1 State diagram conventions 82.2.18.2 State variables 82.2.18.2.1 Constants 82.2.18.2.2 Variables
191	82.2.18.2.3 Functions
192	82.2.18.2.4 Counters
193	82.2.18.2.5 Timers 82.2.18.3 State diagrams
194	82.3 PCS Management 82.3.1 PMD MDIO function mapping
195	82.4 Loopback 82.5 Delay constraints
196	82.6 Auto-Negotiation
202	82.7 Protocol implementation conformance statement (PICS) proforma for Clause 82, Physical Coding Sublayer (PCS) for 64B/66B, type 40GBASE-R and 100GBASE-R 82.7.1 Introduction 82.7.2 Identification 82.7.2.1 Implementation identification 82.7.2.2 Protocol summary
203	82.7.3 Major capabilities/options
204	82.7.4 PICS Proforma Tables for PCS, type 40GBASE-R and 100GBASE-R 82.7.4.1 Coding rules 82.7.4.2 Scrambler and Descrambler
205	82.7.4.3 Deskew and Reordering 82.7.4.4 Alignment Markers 82.7.5 Test-pattern modes
206	82.7.5.1 Bit order 82.7.6 Management
207	82.7.6.1 State diagrams
208	82.7.6.2 Loopback 82.7.6.3 Delay constraints 82.7.6.5 Auto-Negotiation for Backplane Ethernet functions
209	83. Physical Medium Attachment (PMA) sublayer, type 40GBASE-R and 100GBASE-R 83.1 Overview 83.1.1 Scope 83.1.2 Position of the PMA in the 40GBASE-R or 100GBASE-R sublayers 83.1.3 Summary of functions 83.1.4 PMA sublayer positioning
212	83.2 PMA interfaces 83.3 PMA service interface
214	83.4 Service interface below PMA
215	83.5 Functions within the PMA 83.5.1 Per input-lane clock and data recovery 83.5.2 Bit-level multiplexing
218	83.5.3 Skew and Skew Variation 83.5.3.1 Skew generation toward SP1 83.5.3.2 Skew tolerance at SP1 83.5.3.3 Skew generation toward SP2 83.5.3.4 Skew tolerance at SP5 83.5.3.5 Skew generation at SP6
219	83.5.3.6 Skew tolerance at SP6 83.5.4 Delay constraints 83.5.5 Clocking architecture 83.5.6 Signal drivers
220	83.5.7 Link status 83.5.8 PMA local loopback mode 83.5.9 PMA remote loopback mode (optional)
221	83.5.10 PMA test patterns (optional)
222	83.6 PMA MDIO function mapping
227	83.7 Protocol implementation conformance statement (PICS) proforma for Clause 83, Physical Medium Attachment (PMA) sublayer, type 40GBASE-R and 100GBASE-R 83.7.1 Introduction 83.7.2 Identification 83.7.2.1 Implementation identification 83.7.2.2 Protocol summary
228	83.7.3 Major capabilities/options
230	83.7.4 Skew generation and tolerance 83.7.5 Test patterns
231	83.7.6 Loopback modes
233	84. Physical Medium Dependent sublayer and baseband medium, type 40GBASE-KR4 84.1 Overview 84.2 Physical Medium Dependent (PMD) service interface
234	84.3 PCS requirements for Auto-Negotiation (AN) service interface
235	84.4 Delay constraints 84.5 Skew constraints 84.6 PMD MDIO function mapping 84.7 PMD functional specifications 84.7.1 Link block diagram 84.7.2 PMD transmit function
237	84.7.3 PMD receive function 84.7.4 Global PMD signal detect function 84.7.5 PMD lane-by-lane signal detect function 84.7.6 Global PMD transmit disable function
238	84.7.7 PMD lane-by-lane transmit disable function 84.7.8 Loopback mode 84.7.9 PMD_fault function 84.7.10 PMD transmit fault function 84.7.11 PMD receive fault function
239	84.7.12 PMD control function 84.8 40GBASE-KR4 electrical characteristics 84.8.1 Transmitter characteristics 84.8.1.1 Test fixture 84.8.2 Receiver characteristics 84.8.2.1 Receiver interference tolerance 84.9 Interconnect characteristics 84.10 Environmental specifications 84.10.1 General safety
240	84.10.2 Network safety 84.10.3 Installation and maintenance guidelines 84.10.4 Electromagnetic compatibility 84.10.5 Temperature and humidity
241	84.11 Protocol implementation conformance statement (PICS) proforma for Clause 84, Physical Medium Dependent sublayer and baseband medium, type 40GBASE-KR4 84.11.1 Introduction 84.11.2 Identification 84.11.2.1 Implementation identification 84.11.2.2 Protocol summary
242	84.11.3 Major capabilities/options
243	84.11.4 PICS proforma tables for Clause 84, Physical Medium Dependent (PMD) sublayer and baseband medium, type 40GBASE-KR4 84.11.4.1 PMD functional specifications
244	84.11.4.2 Management functions 84.11.4.3 Transmitter electrical characteristics 84.11.4.4 Receiver electrical characteristics
245	84.11.4.5 Environmental specifications
247	85. Physical Medium Dependent sublayer and baseband medium, type 40GBASE-CR4 and 100GBASE-CR10 85.1 Overview
248	85.2 Physical Medium Dependent (PMD) service interface
249	85.3 PCS requirements for Auto-Negotiation (AN) service interface 85.4 Delay constraints 85.5 Skew constraints
250	85.6 PMD MDIO function mapping
252	85.7 PMD functional specifications 85.7.1 Link block diagram
253	85.7.2 PMD Transmit function 85.7.3 PMD Receive function 85.7.4 Global PMD signal detect function
254	85.7.5 PMD lane-by-lane signal detect function 85.7.6 Global PMD transmit disable function 85.7.7 PMD lane-by-lane transmit disable function 85.7.8 Loopback mode
255	85.7.9 PMD_fault function 85.7.10 PMD transmit fault function 85.7.11 PMD receive fault function 85.7.12 PMD control function 85.8 MDI Electrical specifications for 40GBASE-CR4 and 100GBASE-CR10 85.8.1 Signal levels
256	85.8.2 Signal paths 85.8.3 Transmitter characteristics
257	85.8.3.1 Transmitter differential output return loss 85.8.3.2 Transmitter noise parameter measurements
258	85.8.3.3 Transmitter output waveform
260	85.8.3.3.1 Coefficient initialization 85.8.3.3.2 Coefficient step size 85.8.3.3.3 Coefficient range 85.8.3.3.4 Waveform acquisition 85.8.3.3.5 Linear fit to the waveform measurement at TP2
261	85.8.3.3.6 Transfer function between the transmit function and TP2
262	85.8.3.4 Insertion loss TP0 to TP2 or TP3 to TP5
263	85.8.3.5 Test fixture
264	85.8.3.6 Test fixture impedance 85.8.3.7 Test fixture insertion loss 85.8.3.8 Data dependent jitter (DDJ) 85.8.3.9 Signaling rate range
265	85.8.4 Receiver characteristics at TP3 summary 85.8.4.1 Receiver differential input return loss
266	85.8.4.2 Receiver interference tolerance test 85.8.4.2.1 Test setup
267	85.8.4.2.2 Test channel 85.8.4.2.3 Test channel calibration
268	85.8.4.2.4 Pattern generator 85.8.4.2.5 Test procedure 85.8.4.3 Bit error ratio 85.8.4.4 Signaling rate range 85.8.4.5 AC coupling
269	85.9 Channel characteristics 85.10 Cable assembly characteristics 85.10.1 Characteristic impedance and reference impedance 85.10.2 Cable assembly insertion loss
271	85.10.3 Cable assembly insertion loss deviation (ILD)
272	85.10.4 Cable assembly return loss
273	85.10.5 Cable assembly multiple disturber near-end crosstalk (MDNEXT) loss 85.10.6 Cable assembly multiple disturber far-end crosstalk (MDFEXT) loss
274	85.10.7 Cable assembly integrated crosstalk noise (ICN)
276	85.10.8 Cable assembly test fixture 85.10.9 Mated test fixtures
277	85.10.9.1 Mated test fixtures insertion loss 85.10.9.2 Mated test fixtures return loss
278	85.10.9.3 Mated test fixtures common-mode return loss
279	85.10.9.4 Mated test fixtures common-mode conversion loss
280	85.10.9.5 Mated test fixtures integrated crosstalk noise 85.10.10 Shielding 85.10.11 Crossover function
281	85.11 MDI specification 85.11.1 40GBASE-CR4 MDI connectors 85.11.1.1 Style-1 40GBASE-CR4 MDI connectors
282	85.11.1.1.1 Style-1 AC coupling
283	85.11.1.2 Style-2 40GBASE-CR4 MDI connectors 85.11.1.2.1 Style-2 40GBASE-CR4 Connector pin assignments
284	85.11.2 100GBASE-CR10 MDI connectors
286	85.11.2.1 100GBASE-CR10 MDI AC coupling 85.11.3 Electronic keying 85.12 Environmental specifications
287	85.13 Protocol implementation conformance statement (PICS) proforma for Clause 85, Physical Medium Dependent (PMD) sublayer and baseband medium, type 40GBASE-CR4 and 100GBASE-CR10 85.13.1 Introduction 85.13.2 Identification 85.13.2.1 Implementation identification 85.13.2.2 Protocol summary
288	85.13.3 PICS proforma tables for 40GBASE-CR4 and 100GBASE-CR10 PMDs and baseband medium 85.13.4 Major capabilities/options
290	85.13.4.1 PMD functional specifications
291	85.13.4.2 Management functions
292	85.13.4.3 Transmitter specifications 85.13.4.4 Receiver specifications
293	85.13.4.5 Cable assembly specifications
294	85.13.4.6 MDI connector specifications 85.13.4.7 Environmental specifications
295	86. Physical Medium Dependent (PMD) sublayer and medium, type 40GBASE–SR4 and 100GBASE–SR10 86.1 Overview
297	86.2 Physical Medium Dependent (PMD) service interface
298	86.3 Delay and Skew 86.3.1 Delay constraints 86.3.2 Skew and Skew Variation constraints 86.4 PMD MDIO function mapping
299	86.5 PMD functional specifications 86.5.1 PMD block diagram
300	86.5.2 PMD transmit function 86.5.3 PMD receive function 86.5.4 PMD global signal detect function
301	86.5.5 PMD lane-by-lane signal detect function 86.5.6 PMD reset function 86.5.7 PMD global transmit disable function (optional)
302	86.5.8 PMD lane-by-lane transmit disable function (optional) 86.5.9 PMD fault function (optional) 86.5.10 PMD transmit fault function (optional) 86.5.11 PMD receive fault function (optional) 86.6 Lane assignments 86.7 PMD to MDI specifications for 40GBASE-SR4 or 100GBASE-SR10
303	86.7.1 Transmitter optical specifications
304	86.7.2 Characteristics of signal within, and at the receiving end of, a compliant optical channel
305	86.7.3 40GBASE–SR4 or 100GBASE–SR10 receiver optical specifications
306	86.7.4 40GBASE–SR4 or 100GBASE–SR10 illustrative link power budget 86.8 Definitions of optical and dual-use parameters and measurement methods 86.8.1 Test points and compliance boards
308	86.8.2 Test patterns and related subclauses
309	86.8.2.1 Multi-lane testing considerations 86.8.3 Parameters applicable to both electrical and optical signals 86.8.3.1 Skew and Skew Variation
310	86.8.3.2 Eye diagrams 86.8.3.2.1 Eye mask acceptable hit count examples 86.8.3.3 Jitter 86.8.3.3.1 J2 Jitter 86.8.3.3.2 J9 Jitter
311	86.8.4 Optical parameter definitions 86.8.4.1 Wavelength and spectral width 86.8.4.2 Average optical power 86.8.4.3 Optical Modulation Amplitude (OMA) 86.8.4.4 Transmitter and dispersion penalty (TDP) 86.8.4.5 Extinction ratio 86.8.4.6 Transmitter optical waveform (transmit eye)
312	86.8.4.6.1 Optical transmitter eye mask
313	86.8.4.7 Stressed receiver sensitivity 86.8.4.8 Receiver jitter tolerance
314	86.9 Safety, installation, environment, and labeling 86.9.1 General safety 86.9.2 Laser safety 86.9.3 Installation 86.9.4 Environment 86.9.5 PMD labeling 86.10 Optical channel 86.10.1 Fiber optic cabling model
315	86.10.2 Characteristics of the fiber optic cabling (channel) 86.10.2.1 Optical fiber cable 86.10.2.2 Optical fiber connection
316	86.10.2.2.1 Connection insertion loss 86.10.2.2.2 Maximum discrete reflectance 86.10.3 Medium Dependent Interface (MDI) 86.10.3.1 Optical lane assignments for 40GBASE-SR4
317	86.10.3.2 Optical lane assignments for 100GBASE-SR10 86.10.3.3 Medium Dependent Interface (MDI) requirements
319	86.11 Protocol implementation conformance statement (PICS) proforma for Clause 86, Physical Medium Dependent (PMD) sublayer and medium, type 40GBASE–SR4 and 100GBASE–SR10 86.11.1 Introduction 86.11.2 Identification 86.11.2.1 Implementation identification 86.11.2.2 Protocol summary
320	86.11.3 Major capabilities/options
321	86.11.4 PICS proforma tables for Physical Medium Dependent (PMD) sublayer and medium, types 40GBASE–SR4 and 100GBASE–SR10 86.11.4.1 PMD functional specifications
322	86.11.4.2 Management functions 86.11.4.3 Optical specifications for 40GBASE–SR4 or 100GBASE–SR10
323	86.11.4.4 Definitions of parameters and measurement methods 86.11.4.5 Environmental and safety specifications
324	86.11.4.6 Optical channel and MDI
325	87. Physical Medium Dependent (PMD) sublayer and medium, type 40GBASE–LR4 87.1 Overview 87.2 Physical Medium Dependent (PMD) service interface
327	87.3 Delay and Skew 87.3.1 Delay constraints 87.3.2 Skew constraints 87.4 PMD MDIO function mapping 87.5 PMD functional specifications 87.5.1 PMD block diagram
328	87.5.2 PMD transmit function
329	87.5.3 PMD receive function 87.5.4 PMD global signal detect function
330	87.5.5 PMD lane-by-lane signal detect function 87.5.6 PMD reset function 87.5.7 PMD global transmit disable function (optional) 87.5.8 PMD lane-by-lane transmit disable function
331	87.5.9 PMD fault function (optional) 87.5.10 PMD transmit fault function (optional) 87.5.11 PMD receive fault function (optional) 87.6 Wavelength-division-multiplexed lane assignments 87.7 PMD to MDI optical specifications for 40GBASE–LR4
332	87.7.1 40GBASE–LR4 transmitter optical specifications
333	87.7.2 40GBASE–LR4 receive optical specifications 87.7.3 40GBASE–LR4 illustrative link power budget
334	87.8 Definition of optical parameters and measurement methods 87.8.1 Test patterns for optical parameters 87.8.2 Skew and Skew Variation
335	87.8.3 Wavelength 87.8.4 Average optical power 87.8.5 Optical Modulation Amplitude (OMA)
336	87.8.6 Transmitter and dispersion penalty 87.8.6.1 Reference transmitter requirements 87.8.6.2 Channel requirements
337	87.8.6.3 Reference receiver requirements 87.8.6.4 Test procedure 87.8.7 Extinction ratio 87.8.8 Relative Intensity Noise (RIN20OMA) 87.8.9 Transmitter optical waveform (transmit eye)
338	87.8.10 Receiver sensitivity 87.8.11 Stressed receiver sensitivity 87.8.11.1 Stressed receiver conformance test block diagram
339	87.8.11.2 Stressed receiver conformance test signal characteristics and calibration
341	87.8.11.3 Stressed receiver conformance test signal verification 87.8.11.4 Sinusoidal jitter for receiver conformance test
342	87.8.11.5 Stressed receiver conformance test procedure for WDM conformance testing
343	87.8.12 Receiver 3 dB electrical upper cutoff frequency 87.9 Safety, installation, environment, and labeling 87.9.1 General safety 87.9.2 Laser safety
344	87.9.3 Installation 87.9.4 Environment 87.9.4.1 Electromagnetic emission 87.9.4.2 Temperature, humidity, and handling 87.9.5 PMD labeling requirements
345	87.10 Fiber optic cabling model 87.11 Characteristics of the fiber optic cabling (channel)
346	87.11.1 Optical fiber cable 87.11.2 Optical fiber connection 87.11.2.1 Connection insertion loss 87.11.2.2 Maximum discrete reflectance 87.11.3 Medium Dependent Interface (MDI) requirements
347	87.12 Protocol implementation conformance statement (PICS) proforma for Clause 87, Physical Medium Dependent (PMD) sublayer and medium, type 40GBASE-LR4 87.12.1 Introduction 87.12.2 Identification 87.12.2.1 Implementation identification 87.12.2.2 Protocol summary
348	87.12.3 Major capabilities/options
349	87.12.4 PICS proforma tables for Physical Medium Dependent (PMD) sublayer and medium, type 40GBASE-LR4 87.12.4.1 PMD functional specifications
350	87.12.4.2 Management functions 87.12.4.3 PMD to MDI optical specifications for 40GBASE-LR4
351	87.12.4.4 Optical measurement methods 87.12.4.5 Environmental specifications 87.12.4.6 Characteristics of the fiber optic cabling and MDI
353	88. Physical Medium Dependent (PMD) sublayer and medium, type 100GBASE–LR4 and 100GBASE–ER4 88.1 Overview 88.2 Physical Medium Dependent (PMD) service interface
355	88.3 Delay and Skew 88.3.1 Delay constraints 88.3.2 Skew constraints 88.4 PMD MDIO function mapping 88.5 PMD functional specifications 88.5.1 PMD block diagram
357	88.5.2 PMD transmit function 88.5.3 PMD receive function 88.5.4 PMD global signal detect function
358	88.5.5 PMD lane-by-lane signal detect function 88.5.6 PMD reset function 88.5.7 PMD global transmit disable function (optional) 88.5.8 PMD lane-by-lane transmit disable function
359	88.5.9 PMD fault function (optional) 88.5.10 PMD transmit fault function (optional) 88.5.11 PMD receive fault function (optional) 88.6 Wavelength-division-multiplexed lane assignments 88.7 PMD to MDI optical specifications for 100GBASE–LR4 and 100GBASE–ER4
360	88.7.1 100GBASE–LR4 and 100GBASE–ER4 transmitter optical specifications
362	88.7.2 100GBASE–LR4 and 100GBASE–ER4 receive optical specifications
363	88.7.3 100GBASE–LR4 and 100GBASE–ER4 illustrative link power budgets 88.8 Definition of optical parameters and measurement methods 88.8.1 Test patterns for optical parameters 88.8.2 Wavelength
364	88.8.3 Average optical power 88.8.4 Optical Modulation Amplitude (OMA)
365	88.8.5 Transmitter and dispersion penalty (TDP) 88.8.5.1 Reference transmitter requirements 88.8.5.2 Channel requirements
366	88.8.5.3 Reference receiver requirements 88.8.5.4 Test procedure 88.8.6 Extinction ratio 88.8.7 Relative Intensity Noise (RIN20OMA) 88.8.8 Transmitter optical waveform (transmit eye)
367	88.8.9 Receiver sensitivity 88.8.10 Stressed receiver sensitivity 88.8.11 Receiver 3 dB electrical upper cutoff frequency 88.9 Safety, installation, environment, and labeling 88.9.1 General safety 88.9.2 Laser safety
368	88.9.3 Installation 88.9.4 Environment 88.9.5 Electromagnetic emission 88.9.6 Temperature, humidity, and handling 88.9.7 PMD labeling requirements
369	88.10 Fiber optic cabling model 88.11 Characteristics of the fiber optic cabling (channel)
370	88.11.1 Optical fiber cable 88.11.2 Optical fiber connection 88.11.2.1 Connection insertion loss 88.11.2.2 Maximum discrete reflectance 88.11.3 Medium Dependent Interface (MDI) requirements
371	88.12 Protocol implementation conformance statement (PICS) proforma for Clause 88, Physical Medium Dependent (PMD) sublayer and medium, type 100GBASE–LR4 and 100GBASE–ER4 88.12.1 Introduction 88.12.2 Identification 88.12.2.1 Implementation identification 88.12.2.2 Protocol summary
372	88.12.3 Major capabilities/options
373	88.12.4 PICS proforma tables for Physical Medium Dependent (PMD) sublayer and medium, types 100GBASE–LR4 and 100GBASE–ER4 88.12.4.1 PMD functional specifications
374	88.12.4.2 Management functions 88.12.4.3 PMD to MDI optical specifications for 100GBASE–LR4 88.12.4.4 PMD to MDI optical specifications for 100GBASE–ER4
375	88.12.4.5 Optical measurement methods 88.12.4.6 Environmental specifications 88.12.4.7 Characteristics of the fiber optic cabling and MDI
377	Annex A (informative) Bibliography Bibliography
379	Annex 4A (normative) Simplified full duplex media access control Simplified full duplex media access control 4A.4.2 MAC parameters
381	Annex 31B (normative) MAC Control PAUSE operation MAC Control PAUSE operation 31B.3.7 Timing considerations for PAUSE operation
382	31B.4 Protocol implementation conformance statement (PICS) proforma for MAC Control PAUSE operation 31B.4.3 Major capabilities/options
383	31B.4.6 PAUSE command MAC timing considerations
385	Annex 69A (normative) Interference tolerance testing Interference tolerance testing
387	Annex 69B (informative) Interconnect characteristics Interconnect characteristics
391	Annex 83A (normative) 40 Gb/s Attachment Unit Interface (XLAUI) and 100 Gb/s Attachment Unit Interface (CAUI) 40 Gb/s Attachment Unit Interface (XLAUI) and 100 Gb/s Attachment Unit Interface (CAUI) 83A.1 Overview
392	83A.1.1 Summary of major concepts 83A.1.2 Rate of operation 83A.2 XLAUI/CAUI link block diagram
393	83A.2.1 Transmitter compliance points
394	83A.2.2 Receiver compliance points 83A.3 XLAUI/CAUI electrical characteristics 83A.3.1 Signal levels
395	83A.3.2 Signal paths 83A.3.3 Transmitter characteristics 83A.3.3.1 Output amplitude
396	83A.3.3.2 Rise/fall time
397	83A.3.3.3 Differential output return loss 83A.3.3.4 Common-mode output return loss
398	83A.3.3.5 Transmitter eye mask and transmitter jitter definition
399	83A.3.4 Receiver characteristics
400	83A.3.4.1 Bit error ratio 83A.3.4.2 Input signal definition 83A.3.4.3 Differential input return loss
401	83A.3.4.4 Differential to common-mode input return loss
402	83A.3.4.5 AC coupling 83A.3.4.6 Jitter tolerance
403	83A.4 Interconnect characteristics
404	83A.4.1 Characteristic impedance
405	83A.5 Electrical parameter measurement methods 83A.5.1 Transmit jitter 83A.5.2 Receiver tolerance
406	83A.6 Environmental specifications 83A.6.1 General safety 83A.6.2 Network safety 83A.6.3 Installation and maintenance guidelines 83A.6.4 Electromagnetic compatibility 83A.6.5 Temperature and humidity
407	83A.7 Protocol implementation conformance statement (PICS) proforma for Annex 83A, 40 Gb/s Attachment Unit Interface (XLAUI) and 100 Gb/s Attachment Unit Interface (CAUI) 83A.7.1 Introduction 83A.7.2 Identification 83A.7.2.1 Implementation identification 83A.7.2.2 Protocol summary
408	83A.7.3 Major capabilities/options 83A.7.4 XLAUI/CAUI transmitter requirements
409	83A.7.5 XLAUI/CAUI receiver requirements 83A.7.6 Electrical measurement methods 83A.7.7 Environmental specifications
411	Annex 83B (normative) Chip-module 40 Gb/s Attachment Unit Interface (XLAUI) and 100 Gb/s Attachment Unit Interface (CAUI) Chip-module 40 Gb/s Attachment Unit Interface (XLAUI) and 100 Gb/s Attachment Unit Interface (CAUI) 83B.1 Overview
413	83B.2 Compliance point specifications for chip-module XLAUI/CAUI
415	83B.2.1 Module specifications
417	83B.2.2 Host specifications
418	83B.2.3 Host input signal tolerance
419	83B.3 Environmental specifications 83B.3.1 General safety 83B.3.2 Network safety 83B.3.3 Installation and maintenance guidelines 83B.3.4 Electromagnetic compatibility
420	83B.3.5 Temperature and humidity
421	83B.4 Protocol implementation conformance statement (PICS) proforma for Annex 83B, Chip-module 40 Gb/s Attachment Unit Interface (XLAUI) and 100 Gb/s Attachment Unit Interface (CAUI) 83B.4.1 Introduction 83B.4.2 Identification 83B.4.2.1 Implementation identification 83B.4.2.2 Protocol summary
422	83B.4.3 Major capabilities/options 83B.4.4 Module requirements 83B.4.5 Host requirements
423	83B.4.6 Environmental specifications
425	Annex 83C (informative) PMA sublayer partitioning examples PMA sublayer partitioning examples 83C.1 Partitioning examples with FEC 83C.1.1 FEC implemented with PCS
426	83C.1.2 FEC implemented with PMD 83C.2 Partitioning examples without FEC 83C.2.1 Single PMA sublayer without FEC
427	83C.2.2 Single XLAUI/CAUI without FEC 83C.2.3 Separate SERDES for optical module interface
429	Annex 85A (informative) 40GBASE-CR4 and 100GBASE-CR10 TP0 and TP5 test point parameters 40GBASE-CR4 and 100GBASE-CR10 TP0 and TP5 test point parameters 85A.1 Overview 85A.2 Transmitter characteristics at TP0
430	85A.3 Receiver characteristics at TP5 85A.4 Transmitter and receiver differential printed circuit board trace loss
431	85A.5 Channel insertion loss
432	85A.6 Channel return loss 85A.7 Channel insertion loss deviation (ILD)
433	85A.8 Channel integrated crosstalk noise (ICN)
435	Annex 86A (normative) Parallel Physical Interface (nPPI) for 40GBASE-SR4 and 40GBASE-LR4 (XLPPI) and 100GBASE-SR10 (CPPI) Parallel Physical Interface (nPPI) for 40GBASE-SR4 and 40GBASE-LR4 (XLPPI) and 100GBASE-SR10 (CPPI) 86A.1 Overview 86A.2 Block diagram and test points 86A.3 Lane assignments
436	86A.4 Electrical specifications for nPPI 86A.4.1 nPPI host to module electrical specifications
437	86A.4.1.1 Differential return losses at TP1 and TP1a
438	86A.4.1.2 Common-mode output return loss at TP1a 86A.4.2 nPPI module to host electrical specifications 86A.4.2.1 Differential return losses at TP4 and TP4a
439	86A.4.2.2 Common-mode output return loss at TP4 86A.5 Definitions of electrical parameters and measurement methods 86A.5.1 Test points and compliance boards
441	86A.5.1.1 Compliance board parameters 86A.5.1.1.1 Reference insertion losses of HCB and MCB
442	86A.5.1.1.2 Electrical specifications of mated HCB and MCB
444	86A.5.2 Test patterns and related subclauses
445	86A.5.3 Parameter definitions 86A.5.3.1 AC common-mode voltage 86A.5.3.2 Termination mismatch
446	86A.5.3.3 Transition time 86A.5.3.4 Data Dependent Pulse Width Shrinkage (DDPWS)
447	86A.5.3.5 Signal to noise ratio Qsq
448	86A.5.3.6 Eye mask for TP1a and TP4 86A.5.3.7 Reference impedances for electrical measurements 86A.5.3.8 Host input signal tolerance 86A.5.3.8.1 Introduction 86A.5.3.8.2 Test equipment and setup 86A.5.3.8.3 Stressed eye jitter characteristics
450	86A.5.3.8.4 Calibration 86A.5.3.8.5 Calibration procedure
451	86A.5.3.8.6 Test procedure
452	86A.6 Recommended electrical channel
453	86A.7 Safety, installation, environment, and labeling 86A.7.1 General safety 86A.7.2 Installation 86A.7.3 Environment 86A.7.4 PMD labeling
454	86A.8 Protocol implementation conformance statement (PICS) proforma for Annex 86A, Parallel Physical Interface (nPPI) for 40GBASE-SR4 and 40GBASE-LR4 (XLPPI) and 100GBASE-SR10 (CPPI) 86A.8.1 Introduction 86A.8.2 Identification 86A.8.2.1 Implementation identification 86A.8.2.2 Protocol summary
455	86A.8.3 Major capabilities/options 86A.8.4 PICS proforma tables for Parallel Physical Interface (nPPI) for 40GBASE- SR4 and 40GBASE-LR4 (XLPPI) and 100GBASE-SR10 (CPPI) 86A.8.4.1 PMD functional specifications
456	86A.8.4.2 Electrical specifications for nPPI 86A.8.4.3 Definitions of parameters and measurement methods
457	86A.8.4.4 Environmental and safety specifications

Additional information

Standard Title	IEEE Standard for Information technology– Local and metropolitan area networks– Specific requirements– Part 3: CSMA/CD Access Method and Physical Layer Specifications Amendment 4: Media Access Control Parameters, Physical Layers, and Management Parameters for 40 Gb/s and 100 Gb/s Operation
Published Code	IEEE
Publication Date	2010
Pages Count	457

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