BSI PD IEC TR 62878-2-7:2019
$102.76
Device embedding assembly technology – Guidelines. Accelerated stress testing of passive embedded circuit boards
Published By | Publication Date | Number of Pages |
BSI | 2019 | 16 |
This part of IEC 62878 describes the accelerated stress testing of passive embedded circuit boards. It can be used for screening finished boards, including multilayer and high-density interconnection (HDI) boards. These boards are mainly for mobile devices.
PDF Catalog
PDF Pages | PDF Title |
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2 | undefined |
4 | CONTENTS |
5 | FOREWORD |
7 | 1 Scope 2 Normative references 3 Terms and definitions 4 Overview of accelerated stress testing of passive embedded circuit boards 4.1 Testing under combined stresses |
8 | 4.2 Test coupon design Figures Figure 1 – Testing principal Figure 2 – Embedded circuit board panel with test coupons |
9 | Figure 3 – Test coupon structure Tables Table 1 – Design information for test coupon Table 2 – Stack-up information for test coupon |
10 | 5 Test procedure 5.1 General 5.2 Setting test temperature 5.3 Placement of samples on bending tester Figure 4 – Opened and closed sample jig |
11 | 5.4 Imposing combined stresses 5.5 Evaluation of results Figure 5 – Bending of test coupons |
12 | 6 Results Figure 6 – Output voltage Figure 7 – Cross section of sample after testing Figure 8 – Cross section of failed sample Table 3 – Coupon testing results |
13 | Annex A (informative)Test coupon design rule Table A.1 – Test coupon design rules |
14 | Annex B (informative)Bending testing Figure B.1 – Bending tester in the chamber |