This Technical Report provides information when using semiconductor devices in wider temperature ranges than those specified by the device manufacturer. The uprating solutions described herein are considered exceptions, when no reasonable alternatives are available; otherwise devices are utilized within the manufacturers’ specifications.

The terms “uprating” and “thermal uprating” are being used increasingly in avionics industry discussions and meetings, and clear definitions are included in Clause 3. They were coined as shorthand references to a special case of methods commonly used in selecting components for circuit design.

This technical report describes the methods and processes for implementing this special case.

All of the elements of these methods and processes employ existing, commonly used best engineering practices. No new or unique engineering knowledge is needed to follow these processes: only a rigorous application of the overall approach.

Even though the device is used at wider temperatures, the wider temperatures usage will be limited to those that do not compromise applications performance and reliability, particularly for devices with narrow feature size geometries (e.g., 90 nm and less). This technical report does not imply that applications use the device to function beyond the absolute maximum rating limits of the device specified by the original device manufacturer and assumes that:

device usage outside the original device manufacturers’ specified temperature ranges is done only when no reasonable alternative approach is available and is performed with appropriate justification;
if it is necessary to use devices outside the original device manufacturers’ specified temperature ranges, it is done with documented and controlled processes that assure integrity of the equipment.

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PDF Pages	PDF Title
4	CONTENTS
6	FOREWORD
8	INTRODUCTION
9	1 Scope 2 Normative references 3 Terms, definitions and abbreviations 3.1 Terms and definitions
12	3.2 Abbreviations 4 Selection provisions 4.1 General 4.2 Device selection, usage and alternatives 4.2.1 General
13	4.2.2 Alternatives 4.2.3 Device technology 4.2.4 Compliance with the electronic component management plan
14	4.3 Device capability assessment 4.3.1 General 4.3.2 Device package and internal construction capability assessment 4.3.3 Risk assessment (assembly level)
15	4.3.4 Device uprating methods
16	4.3.5 Device reliability assurance
17	4.4 Device quality assurance in wider temperature ranges 4.4.1 General 4.4.2 Device parameter re-characterisation testing 4.4.3 Device parameter conformance testing 4.4.4 Higher assembly level testing
18	4.4.5 Semiconductor device change monitoring 4.4.6 Failure data collection and analysis 4.5 Documentation 4.6 Device identification
20	Figure 1 – Flow chart for semiconductor devices in wider temperature ranges
21	Figure 2 – Report form for documenting device usage in wider temperature ranges
22	Annex A (informative)Device parameter re-characterisation
23	Figure A.1 – Parameter re-characterisation
25	Figure A.2 – Flow diagram of parameter re-characterisation capability assurance process
26	Table A.1 – Example of sample size calculation
28	Figure A.3 – Margin in electrical parameter measurement based on the results of the sample test
29	Figure A.4 – Schematic diagram of parameter limit modifications Table A.2 – Parameter re-characterisation example: SN74ALS244 Octal Buffer/Driver
30	Figure A.5 – Parameter re-characterisation device quality assurance
31	Figure A.6 – Schematic of outlier products that may invalidate sample testing
32	Figure A.7 – Example of intermediate peak of an electrical parameter: voltage feedback input threshold change for Motorola MC34261 power factor controller [4]
33	Figure A.8 – Report form for documenting device parameter re-characterisation
34	Annex B (informative)Stress balancing
36	Figure B.1 – Iso-TJ curve: the relationship between ambient temperature and dissipated power
37	Figure B.2 – Graph of electrical parameters versus dissipated power
40	Figure B.3 – Iso-TJ curve for the Fairchild MM74HC244
41	Figure B.4 – Power versus frequency curve for the Fairchild MM74HC244
42	Figure B.5 – Flow chart for stress balancing
43	Figure B.6 – Report form for documenting stress balancing
44	Annex C (informative)Parameter conformance assessment
45	Figure C.1 – Relationship of temperature ratings, requirements and margins
47	Figure C.2 – Typical fallout distribution versus Treq-max
49	Figure C.3 – Parameter conformance assessment flow
50	Figure C.4 – Report form for documenting parameter conformance testing
51	Annex D (informative)Higher assembly level testing
52	Figure D.1 – Flow chart of higher level assembly testing
53	Figure D.2 – Report form for documenting higher level assembly test at temperature extremes
54	Bibliography Figures Tables

Published By	Publication Date	Number of Pages
BSI	2013	56


PDF Format	Searchable	Printable	Preview Now

Status	Withdrawn
Title	Process management for avionics. Electronic components capability in operation – Temperature uprating
Replaces	PD IEC/TR 62240:2005
Publisher	BSI
Committee	GEL/107
Pages	56
Publication Date	2013-04-23
Withdrawn Date	2018-04-11
Replaced By	PD IEC/TR 62240-1:2018
ISBN	978 0 580 81608 6
Standard Number	PD IEC/TR 62240-1:2013
Identical National Standard Of	IEC TR 62240-1:2013
Descriptors	Semiconductors, Temperature, Performance, Operating conditions, Electronic equipment and components, Overheating, Semiconductor devices, Integrated circuits
ICS Codes	49.060 - Aerospace electric equipment and systems

BSI PD IEC/TR 62240-1:2013

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